331 lines
8.1 KiB
C
331 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2019-2020 Realtek Corporation
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*/
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#include "debug.h"
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#include "efuse.h"
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#include "mac.h"
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#include "reg.h"
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enum rtw89_efuse_bank {
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RTW89_EFUSE_BANK_WIFI,
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RTW89_EFUSE_BANK_BT,
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};
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static int rtw89_switch_efuse_bank(struct rtw89_dev *rtwdev,
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enum rtw89_efuse_bank bank)
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{
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u8 val;
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if (rtwdev->chip->chip_id != RTL8852A)
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return 0;
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val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
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B_AX_EF_CELL_SEL_MASK);
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if (bank == val)
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return 0;
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rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK,
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bank);
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val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
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B_AX_EF_CELL_SEL_MASK);
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if (bank == val)
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return 0;
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return -EBUSY;
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}
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static void rtw89_enable_otp_burst_mode(struct rtw89_dev *rtwdev, bool en)
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{
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if (en)
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rtw89_write32_set(rtwdev, R_AX_EFUSE_CTRL_1_V1, B_AX_EF_BURST);
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else
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rtw89_write32_clr(rtwdev, R_AX_EFUSE_CTRL_1_V1, B_AX_EF_BURST);
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}
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static void rtw89_enable_efuse_pwr_cut_ddv(struct rtw89_dev *rtwdev)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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struct rtw89_hal *hal = &rtwdev->hal;
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if (chip_id == RTL8852A)
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return;
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rtw89_write8_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
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fsleep(1000);
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rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
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rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
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if (chip_id == RTL8852B && hal->cv == CHIP_CAV)
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rtw89_enable_otp_burst_mode(rtwdev, true);
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}
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static void rtw89_disable_efuse_pwr_cut_ddv(struct rtw89_dev *rtwdev)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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struct rtw89_hal *hal = &rtwdev->hal;
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if (chip_id == RTL8852A)
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return;
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if (chip_id == RTL8852B && hal->cv == CHIP_CAV)
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rtw89_enable_otp_burst_mode(rtwdev, false);
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rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
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rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
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fsleep(1000);
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rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
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rtw89_write8_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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}
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static int rtw89_dump_physical_efuse_map_ddv(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size)
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{
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u32 efuse_ctl;
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u32 addr;
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int ret;
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rtw89_enable_efuse_pwr_cut_ddv(rtwdev);
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for (addr = dump_addr; addr < dump_addr + dump_size; addr++) {
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efuse_ctl = u32_encode_bits(addr, B_AX_EF_ADDR_MASK);
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rtw89_write32(rtwdev, R_AX_EFUSE_CTRL, efuse_ctl & ~B_AX_EF_RDY);
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ret = read_poll_timeout_atomic(rtw89_read32, efuse_ctl,
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efuse_ctl & B_AX_EF_RDY, 1, 1000000,
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true, rtwdev, R_AX_EFUSE_CTRL);
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if (ret)
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return -EBUSY;
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*map++ = (u8)(efuse_ctl & 0xff);
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}
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rtw89_disable_efuse_pwr_cut_ddv(rtwdev);
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return 0;
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}
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static int rtw89_dump_physical_efuse_map_dav(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size)
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{
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u32 addr;
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u8 val8;
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int err;
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int ret;
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for (addr = dump_addr; addr < dump_addr + dump_size; addr++) {
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_LOW_ADDR,
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addr & 0xff, XTAL_SI_LOW_ADDR_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, addr >> 8,
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XTAL_SI_HIGH_ADDR_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0,
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XTAL_SI_MODE_SEL_MASK);
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if (ret)
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return ret;
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ret = read_poll_timeout_atomic(rtw89_mac_read_xtal_si, err,
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!err && (val8 & XTAL_SI_RDY),
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1, 10000, false,
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rtwdev, XTAL_SI_CTRL, &val8);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read dav efuse\n");
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return ret;
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}
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ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_READ_VAL, &val8);
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if (ret)
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return ret;
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*map++ = val8;
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}
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return 0;
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}
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static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size, bool dav)
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{
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int ret;
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if (!map || dump_size == 0)
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return 0;
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rtw89_switch_efuse_bank(rtwdev, RTW89_EFUSE_BANK_WIFI);
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if (dav) {
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ret = rtw89_dump_physical_efuse_map_dav(rtwdev, map, dump_addr, dump_size);
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if (ret)
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return ret;
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} else {
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ret = rtw89_dump_physical_efuse_map_ddv(rtwdev, map, dump_addr, dump_size);
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if (ret)
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return ret;
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}
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return 0;
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}
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#define invalid_efuse_header(hdr1, hdr2) \
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((hdr1) == 0xff || (hdr2) == 0xff)
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#define invalid_efuse_content(word_en, i) \
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(((word_en) & BIT(i)) != 0x0)
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#define get_efuse_blk_idx(hdr1, hdr2) \
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((((hdr2) & 0xf0) >> 4) | (((hdr1) & 0x0f) << 4))
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#define block_idx_to_logical_idx(blk_idx, i) \
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(((blk_idx) << 3) + ((i) << 1))
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static int rtw89_dump_logical_efuse_map(struct rtw89_dev *rtwdev, u8 *phy_map,
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u8 *log_map)
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{
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u32 physical_size = rtwdev->chip->physical_efuse_size;
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u32 logical_size = rtwdev->chip->logical_efuse_size;
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u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size;
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u32 phy_idx = sec_ctrl_size;
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u32 log_idx;
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u8 hdr1, hdr2;
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u8 blk_idx;
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u8 word_en;
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int i;
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if (!phy_map)
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return 0;
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while (phy_idx < physical_size - sec_ctrl_size) {
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hdr1 = phy_map[phy_idx];
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hdr2 = phy_map[phy_idx + 1];
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if (invalid_efuse_header(hdr1, hdr2))
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break;
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blk_idx = get_efuse_blk_idx(hdr1, hdr2);
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word_en = hdr2 & 0xf;
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phy_idx += 2;
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for (i = 0; i < 4; i++) {
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if (invalid_efuse_content(word_en, i))
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continue;
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log_idx = block_idx_to_logical_idx(blk_idx, i);
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if (phy_idx + 1 > physical_size - sec_ctrl_size - 1 ||
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log_idx + 1 > logical_size)
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return -EINVAL;
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log_map[log_idx] = phy_map[phy_idx];
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log_map[log_idx + 1] = phy_map[phy_idx + 1];
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phy_idx += 2;
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}
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}
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return 0;
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}
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int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev)
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{
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u32 phy_size = rtwdev->chip->physical_efuse_size;
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u32 log_size = rtwdev->chip->logical_efuse_size;
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u32 dav_phy_size = rtwdev->chip->dav_phy_efuse_size;
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u32 dav_log_size = rtwdev->chip->dav_log_efuse_size;
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u32 full_log_size = log_size + dav_log_size;
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u8 *phy_map = NULL;
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u8 *log_map = NULL;
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u8 *dav_phy_map = NULL;
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u8 *dav_log_map = NULL;
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int ret;
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if (rtw89_read16(rtwdev, R_AX_SYS_WL_EFUSE_CTRL) & B_AX_AUTOLOAD_SUS)
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rtwdev->efuse.valid = true;
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else
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rtw89_warn(rtwdev, "failed to check efuse autoload\n");
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phy_map = kmalloc(phy_size, GFP_KERNEL);
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log_map = kmalloc(full_log_size, GFP_KERNEL);
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if (dav_phy_size && dav_log_size) {
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dav_phy_map = kmalloc(dav_phy_size, GFP_KERNEL);
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dav_log_map = log_map + log_size;
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}
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if (!phy_map || !log_map || (dav_phy_size && !dav_phy_map)) {
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ret = -ENOMEM;
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goto out_free;
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}
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ret = rtw89_dump_physical_efuse_map(rtwdev, phy_map, 0, phy_size, false);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse physical map\n");
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goto out_free;
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}
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ret = rtw89_dump_physical_efuse_map(rtwdev, dav_phy_map, 0, dav_phy_size, true);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse dav physical map\n");
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goto out_free;
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}
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memset(log_map, 0xff, full_log_size);
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ret = rtw89_dump_logical_efuse_map(rtwdev, phy_map, log_map);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse logical map\n");
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goto out_free;
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}
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ret = rtw89_dump_logical_efuse_map(rtwdev, dav_phy_map, dav_log_map);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse dav logical map\n");
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goto out_free;
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}
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rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "log_map: ", log_map, full_log_size);
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ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read efuse map\n");
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goto out_free;
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}
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out_free:
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kfree(dav_phy_map);
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kfree(log_map);
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kfree(phy_map);
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return ret;
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}
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int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev)
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{
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u32 phycap_addr = rtwdev->chip->phycap_addr;
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u32 phycap_size = rtwdev->chip->phycap_size;
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u8 *phycap_map = NULL;
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int ret = 0;
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if (!phycap_size)
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return 0;
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phycap_map = kmalloc(phycap_size, GFP_KERNEL);
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if (!phycap_map)
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return -ENOMEM;
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ret = rtw89_dump_physical_efuse_map(rtwdev, phycap_map,
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phycap_addr, phycap_size, false);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump phycap map\n");
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goto out_free;
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}
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ret = rtwdev->chip->ops->read_phycap(rtwdev, phycap_map);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read phycap map\n");
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goto out_free;
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}
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out_free:
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kfree(phycap_map);
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return ret;
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}
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