385 lines
9.7 KiB
C
385 lines
9.7 KiB
C
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/*
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* NXP Wireless LAN device driver: SDIO specific definitions
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*
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* Copyright 2011-2020 NXP
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*
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* This software file (the "File") is distributed by NXP
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* under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_SDIO_H
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#define _MWIFIEX_SDIO_H
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#include <linux/completion.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/sdio_ids.h>
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#include <linux/mmc/sdio_func.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include "main.h"
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#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
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#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
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#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
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#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
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#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
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#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
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#define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
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#define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
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#define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
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#define BLOCK_MODE 1
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#define BYTE_MODE 0
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#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
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#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
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#define MWIFIEX_MAX_FUNC2_REG_NUM 13
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#define MWIFIEX_SDIO_SCRATCH_SIZE 10
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#define SDIO_MPA_ADDR_BASE 0x1000
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#define CTRL_PORT 0
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#define CTRL_PORT_MASK 0x0001
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#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
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#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
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#define HOST_TERM_CMD53 (0x1U << 2)
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#define REG_PORT 0
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#define MEM_PORT 0x10000
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#define CMD53_NEW_MODE (0x1U << 0)
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#define CMD_PORT_RD_LEN_EN (0x1U << 2)
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#define CMD_PORT_AUTO_EN (0x1U << 0)
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#define CMD_PORT_SLCT 0x8000
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#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
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#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
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#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
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#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
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/* we leave one block of 256 bytes for DMA alignment*/
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#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
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/* Misc. Config Register : Auto Re-enable interrupts */
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#define AUTO_RE_ENABLE_INT BIT(4)
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/* Host Control Registers : Configuration */
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#define CONFIGURATION_REG 0x00
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/* Host Control Registers : Host power up */
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#define HOST_POWER_UP (0x1U << 1)
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/* Host Control Registers : Upload host interrupt mask */
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#define UP_LD_HOST_INT_MASK (0x1U)
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/* Host Control Registers : Download host interrupt mask */
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#define DN_LD_HOST_INT_MASK (0x2U)
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/* Host Control Registers : Upload host interrupt status */
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#define UP_LD_HOST_INT_STATUS (0x1U)
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/* Host Control Registers : Download host interrupt status */
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#define DN_LD_HOST_INT_STATUS (0x2U)
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/* Host Control Registers : Host interrupt status */
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#define CARD_INT_STATUS_REG 0x28
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/* Card Control Registers : Card I/O ready */
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#define CARD_IO_READY (0x1U << 3)
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/* Card Control Registers : Download card ready */
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#define DN_LD_CARD_RDY (0x1U << 0)
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/* Max retry number of CMD53 write */
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#define MAX_WRITE_IOMEM_RETRY 2
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/* SDIO Tx aggregation in progress ? */
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#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
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/* SDIO Tx aggregation buffer room for next packet ? */
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#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
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<= a->mpa_tx.buf_size)
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/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
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#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
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memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
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payload, pkt_len); \
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a->mpa_tx.buf_len += pkt_len; \
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if (!a->mpa_tx.pkt_cnt) \
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a->mpa_tx.start_port = port; \
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if (a->mpa_tx.start_port <= port) \
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a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
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else \
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a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
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(a->max_ports - \
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a->mp_end_port))); \
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a->mpa_tx.pkt_cnt++; \
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} while (0)
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/* SDIO Tx aggregation limit ? */
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#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
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(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
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/* Reset SDIO Tx aggregation buffer parameters */
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#define MP_TX_AGGR_BUF_RESET(a) do { \
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a->mpa_tx.pkt_cnt = 0; \
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a->mpa_tx.buf_len = 0; \
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a->mpa_tx.ports = 0; \
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a->mpa_tx.start_port = 0; \
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} while (0)
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/* SDIO Rx aggregation limit ? */
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#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
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(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
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/* SDIO Rx aggregation in progress ? */
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#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
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/* SDIO Rx aggregation buffer room for next packet ? */
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#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
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((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
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/* Reset SDIO Rx aggregation buffer parameters */
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#define MP_RX_AGGR_BUF_RESET(a) do { \
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a->mpa_rx.pkt_cnt = 0; \
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a->mpa_rx.buf_len = 0; \
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a->mpa_rx.ports = 0; \
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a->mpa_rx.start_port = 0; \
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} while (0)
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/* data structure for SDIO MPA TX */
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struct mwifiex_sdio_mpa_tx {
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/* multiport tx aggregation buffer pointer */
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u8 *buf;
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u32 buf_len;
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u32 pkt_cnt;
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u32 ports;
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u16 start_port;
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u8 enabled;
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u32 buf_size;
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u32 pkt_aggr_limit;
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};
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struct mwifiex_sdio_mpa_rx {
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u8 *buf;
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u32 buf_len;
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u32 pkt_cnt;
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u32 ports;
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u16 start_port;
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struct sk_buff **skb_arr;
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u32 *len_arr;
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u8 enabled;
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u32 buf_size;
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u32 pkt_aggr_limit;
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};
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int mwifiex_bus_register(void);
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void mwifiex_bus_unregister(void);
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struct mwifiex_sdio_card_reg {
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u8 start_rd_port;
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u8 start_wr_port;
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u8 base_0_reg;
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u8 base_1_reg;
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u8 poll_reg;
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u8 host_int_enable;
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u8 host_int_rsr_reg;
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u8 host_int_status_reg;
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u8 host_int_mask_reg;
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u8 status_reg_0;
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u8 status_reg_1;
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u8 sdio_int_mask;
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u32 data_port_mask;
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u8 io_port_0_reg;
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u8 io_port_1_reg;
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u8 io_port_2_reg;
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u8 max_mp_regs;
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u8 rd_bitmap_l;
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u8 rd_bitmap_u;
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u8 rd_bitmap_1l;
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u8 rd_bitmap_1u;
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u8 wr_bitmap_l;
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u8 wr_bitmap_u;
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u8 wr_bitmap_1l;
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u8 wr_bitmap_1u;
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u8 rd_len_p0_l;
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u8 rd_len_p0_u;
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u8 card_misc_cfg_reg;
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u8 card_cfg_2_1_reg;
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u8 cmd_rd_len_0;
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u8 cmd_rd_len_1;
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u8 cmd_rd_len_2;
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u8 cmd_rd_len_3;
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u8 cmd_cfg_0;
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u8 cmd_cfg_1;
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u8 cmd_cfg_2;
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u8 cmd_cfg_3;
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u8 fw_dump_host_ready;
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u8 fw_dump_ctrl;
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u8 fw_dump_start;
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u8 fw_dump_end;
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u8 func1_dump_reg_start;
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u8 func1_dump_reg_end;
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u8 func1_scratch_reg;
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u8 func1_spec_reg_num;
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u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
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};
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struct sdio_mmc_card {
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struct sdio_func *func;
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struct mwifiex_adapter *adapter;
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struct completion fw_done;
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const char *firmware;
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const struct mwifiex_sdio_card_reg *reg;
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u8 max_ports;
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u8 mp_agg_pkt_limit;
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u16 tx_buf_size;
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u32 mp_tx_agg_buf_size;
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u32 mp_rx_agg_buf_size;
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u32 mp_rd_bitmap;
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u32 mp_wr_bitmap;
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u16 mp_end_port;
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u32 mp_data_port_mask;
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u8 curr_rd_port;
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u8 curr_wr_port;
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u8 *mp_regs;
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bool supports_sdio_new_mode;
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bool has_control_mask;
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bool can_dump_fw;
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bool fw_dump_enh;
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bool can_auto_tdls;
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bool can_ext_scan;
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struct mwifiex_sdio_mpa_tx mpa_tx;
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struct mwifiex_sdio_mpa_rx mpa_rx;
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struct work_struct work;
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unsigned long work_flags;
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};
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struct mwifiex_sdio_device {
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const char *firmware;
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const struct mwifiex_sdio_card_reg *reg;
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u8 max_ports;
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u8 mp_agg_pkt_limit;
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u16 tx_buf_size;
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u32 mp_tx_agg_buf_size;
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u32 mp_rx_agg_buf_size;
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bool supports_sdio_new_mode;
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bool has_control_mask;
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bool can_dump_fw;
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bool fw_dump_enh;
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bool can_auto_tdls;
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bool can_ext_scan;
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};
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/*
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* .cmdrsp_complete handler
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*/
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static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
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struct sk_buff *skb)
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{
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dev_kfree_skb_any(skb);
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return 0;
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}
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/*
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* .event_complete handler
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*/
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static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
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struct sk_buff *skb)
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{
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dev_kfree_skb_any(skb);
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return 0;
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}
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static inline bool
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mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
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{
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u8 tmp;
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if (card->curr_rd_port < card->mpa_rx.start_port) {
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if (card->supports_sdio_new_mode)
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tmp = card->mp_end_port >> 1;
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else
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tmp = card->mp_agg_pkt_limit;
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if (((card->max_ports - card->mpa_rx.start_port) +
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card->curr_rd_port) >= tmp)
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return true;
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}
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if (!card->supports_sdio_new_mode)
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return false;
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if ((card->curr_rd_port - card->mpa_rx.start_port) >=
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(card->mp_end_port >> 1))
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return true;
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return false;
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}
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static inline bool
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mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
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{
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u16 tmp;
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if (card->curr_wr_port < card->mpa_tx.start_port) {
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if (card->supports_sdio_new_mode)
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tmp = card->mp_end_port >> 1;
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else
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tmp = card->mp_agg_pkt_limit;
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if (((card->max_ports - card->mpa_tx.start_port) +
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card->curr_wr_port) >= tmp)
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!card->supports_sdio_new_mode)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if ((card->curr_wr_port - card->mpa_tx.start_port) >=
|
||
|
|
(card->mp_end_port >> 1))
|
||
|
|
return true;
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
|
||
|
|
static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
|
||
|
|
u16 rx_len, u8 port)
|
||
|
|
{
|
||
|
|
card->mpa_rx.buf_len += rx_len;
|
||
|
|
|
||
|
|
if (!card->mpa_rx.pkt_cnt)
|
||
|
|
card->mpa_rx.start_port = port;
|
||
|
|
|
||
|
|
if (card->supports_sdio_new_mode) {
|
||
|
|
card->mpa_rx.ports |= (1 << port);
|
||
|
|
} else {
|
||
|
|
if (card->mpa_rx.start_port <= port)
|
||
|
|
card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
|
||
|
|
else
|
||
|
|
card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
|
||
|
|
}
|
||
|
|
card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
|
||
|
|
card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
|
||
|
|
card->mpa_rx.pkt_cnt++;
|
||
|
|
}
|
||
|
|
#endif /* _MWIFIEX_SDIO_H */
|