94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2021 Google, Inc.
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*/
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#ifndef _GVE_DQO_H_
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#define _GVE_DQO_H_
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#include "gve_adminq.h"
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#define GVE_ITR_ENABLE_BIT_DQO BIT(0)
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#define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)
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#define GVE_ITR_NO_UPDATE_DQO (3 << 3)
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#define GVE_ITR_INTERVAL_DQO_SHIFT 5
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#define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)
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#define GVE_TX_IRQ_RATELIMIT_US_DQO 50
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#define GVE_RX_IRQ_RATELIMIT_US_DQO 20
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#define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2)
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/* Timeout in seconds to wait for a reinjection completion after receiving
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* its corresponding miss completion.
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*/
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#define GVE_REINJECT_COMPL_TIMEOUT 1
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/* Timeout in seconds to deallocate the completion tag for a packet that was
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* prematurely freed for not receiving a valid completion. This should be large
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* enough to rule out the possibility of receiving the corresponding valid
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* completion after this interval.
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*/
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#define GVE_DEALLOCATE_COMPL_TIMEOUT 60
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netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);
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bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);
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int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);
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int gve_tx_alloc_rings_dqo(struct gve_priv *priv);
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void gve_tx_free_rings_dqo(struct gve_priv *priv);
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int gve_rx_alloc_rings_dqo(struct gve_priv *priv);
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void gve_rx_free_rings_dqo(struct gve_priv *priv);
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int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,
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struct napi_struct *napi);
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void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);
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void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);
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static inline void
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gve_tx_put_doorbell_dqo(const struct gve_priv *priv,
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const struct gve_queue_resources *q_resources, u32 val)
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{
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u64 index;
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index = be32_to_cpu(q_resources->db_index);
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iowrite32(val, &priv->db_bar2[index]);
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}
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/* Builds register value to write to DQO IRQ doorbell to enable with specified
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* ITR interval.
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*/
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static inline u32 gve_setup_itr_interval_dqo(u32 interval_us)
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{
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u32 result = GVE_ITR_ENABLE_BIT_DQO;
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/* Interval has 2us granularity. */
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interval_us >>= 1;
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interval_us &= GVE_ITR_INTERVAL_DQO_MASK;
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result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT);
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return result;
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}
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static inline void
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gve_write_irq_doorbell_dqo(const struct gve_priv *priv,
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const struct gve_notify_block *block, u32 val)
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{
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u32 index = be32_to_cpu(*block->irq_db_index);
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iowrite32(val, &priv->db_bar2[index]);
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}
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/* Sets interrupt throttling interval and enables interrupt
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* by writing to IRQ doorbell.
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*/
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static inline void
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gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv,
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struct gve_notify_block *block,
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u32 usecs)
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{
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gve_write_irq_doorbell_dqo(priv, block,
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gve_setup_itr_interval_dqo(usecs));
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}
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#endif /* _GVE_DQO_H_ */
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