265 lines
10 KiB
C
265 lines
10 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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#ifndef _FUNETH_TXRX_H
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#define _FUNETH_TXRX_H
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#include <linux/netdevice.h>
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#include <linux/u64_stats_sync.h>
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/* Tx descriptor size */
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#define FUNETH_SQE_SIZE 64U
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/* Size of device headers per Tx packet */
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#define FUNETH_FUNOS_HDR_SZ (sizeof(struct fun_eth_tx_req))
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/* Number of gather list entries per Tx descriptor */
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#define FUNETH_GLE_PER_DESC (FUNETH_SQE_SIZE / sizeof(struct fun_dataop_gl))
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/* Max gather list size in bytes for an sk_buff. */
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#define FUNETH_MAX_GL_SZ ((MAX_SKB_FRAGS + 1) * sizeof(struct fun_dataop_gl))
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#if IS_ENABLED(CONFIG_TLS_DEVICE)
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# define FUNETH_TLS_SZ sizeof(struct fun_eth_tls)
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#else
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# define FUNETH_TLS_SZ 0
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#endif
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/* Max number of Tx descriptors for an sk_buff using a gather list. */
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#define FUNETH_MAX_GL_DESC \
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DIV_ROUND_UP((FUNETH_FUNOS_HDR_SZ + FUNETH_MAX_GL_SZ + FUNETH_TLS_SZ), \
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FUNETH_SQE_SIZE)
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/* Max number of Tx descriptors for any packet. */
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#define FUNETH_MAX_PKT_DESC FUNETH_MAX_GL_DESC
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/* Rx CQ descriptor size. */
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#define FUNETH_CQE_SIZE 64U
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/* Offset of cqe_info within a CQE. */
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#define FUNETH_CQE_INFO_OFFSET (FUNETH_CQE_SIZE - sizeof(struct fun_cqe_info))
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/* Construct the IRQ portion of a CQ doorbell. The resulting value arms the
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* interrupt with the supplied time delay and packet count moderation settings.
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*/
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#define FUN_IRQ_CQ_DB(usec, pkts) \
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(FUN_DB_IRQ_ARM_F | ((usec) << FUN_DB_INTCOAL_USEC_S) | \
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((pkts) << FUN_DB_INTCOAL_ENTRIES_S))
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/* As above for SQ doorbells. */
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#define FUN_IRQ_SQ_DB(usec, pkts) \
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(FUN_DB_IRQ_ARM_F | \
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((usec) << FUN_DB_INTCOAL_USEC_S) | \
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((pkts) << FUN_DB_INTCOAL_ENTRIES_S))
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/* Per packet tailroom. Present only for 1-frag packets. */
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#define FUN_RX_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
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/* Per packet headroom for XDP. Preferred over XDP_PACKET_HEADROOM to
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* accommodate two packets per buffer for 4K pages and 1500B MTUs.
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*/
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#define FUN_XDP_HEADROOM 192
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/* Initialization state of a queue. */
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enum {
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FUN_QSTATE_DESTROYED, /* what queue? */
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FUN_QSTATE_INIT_SW, /* exists in SW, not on the device */
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FUN_QSTATE_INIT_FULL, /* exists both in SW and on device */
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};
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/* Initialization state of an interrupt. */
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enum {
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FUN_IRQ_INIT, /* initialized and in the XArray but inactive */
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FUN_IRQ_REQUESTED, /* request_irq() done */
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FUN_IRQ_ENABLED, /* processing enabled */
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FUN_IRQ_DISABLED, /* processing disabled */
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};
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struct bpf_prog;
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struct funeth_txq_stats { /* per Tx queue SW counters */
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u64 tx_pkts; /* # of Tx packets */
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u64 tx_bytes; /* total bytes of Tx packets */
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u64 tx_cso; /* # of packets with checksum offload */
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u64 tx_tso; /* # of non-encapsulated TSO super-packets */
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u64 tx_encap_tso; /* # of encapsulated TSO super-packets */
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u64 tx_more; /* # of DBs elided due to xmit_more */
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u64 tx_nstops; /* # of times the queue has stopped */
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u64 tx_nrestarts; /* # of times the queue has restarted */
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u64 tx_map_err; /* # of packets dropped due to DMA mapping errors */
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u64 tx_xdp_full; /* # of XDP packets that could not be enqueued */
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u64 tx_tls_pkts; /* # of Tx TLS packets offloaded to HW */
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u64 tx_tls_bytes; /* Tx bytes of HW-handled TLS payload */
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u64 tx_tls_fallback; /* attempted Tx TLS offloads punted to SW */
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u64 tx_tls_drops; /* attempted Tx TLS offloads dropped */
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};
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struct funeth_tx_info { /* per Tx descriptor state */
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union {
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struct sk_buff *skb; /* associated packet */
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void *vaddr; /* start address for XDP */
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};
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};
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struct funeth_txq {
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/* RO cacheline of frequently accessed data */
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u32 mask; /* queue depth - 1 */
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u32 hw_qid; /* device ID of the queue */
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void *desc; /* base address of descriptor ring */
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struct funeth_tx_info *info;
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struct device *dma_dev; /* device for DMA mappings */
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volatile __be64 *hw_wb; /* HW write-back location */
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u32 __iomem *db; /* SQ doorbell register address */
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struct netdev_queue *ndq;
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dma_addr_t dma_addr; /* DMA address of descriptor ring */
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/* producer R/W cacheline */
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u16 qidx; /* queue index within net_device */
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u16 ethid;
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u32 prod_cnt; /* producer counter */
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struct funeth_txq_stats stats;
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/* shared R/W cacheline, primarily accessed by consumer */
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u32 irq_db_val; /* value written to IRQ doorbell */
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u32 cons_cnt; /* consumer (cleanup) counter */
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struct net_device *netdev;
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struct fun_irq *irq;
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int numa_node;
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u8 init_state; /* queue initialization state */
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struct u64_stats_sync syncp;
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};
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struct funeth_rxq_stats { /* per Rx queue SW counters */
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u64 rx_pkts; /* # of received packets, including SW drops */
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u64 rx_bytes; /* total size of received packets */
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u64 rx_cso; /* # of packets with checksum offload */
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u64 rx_bufs; /* total # of Rx buffers provided to device */
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u64 gro_pkts; /* # of GRO superpackets */
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u64 gro_merged; /* # of pkts merged into existing GRO superpackets */
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u64 rx_page_alloc; /* # of page allocations for Rx buffers */
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u64 rx_budget; /* NAPI iterations that exhausted their budget */
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u64 rx_mem_drops; /* # of packets dropped due to memory shortage */
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u64 rx_map_err; /* # of page DMA mapping errors */
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u64 xdp_drops; /* XDP_DROPped packets */
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u64 xdp_tx; /* successful XDP transmits */
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u64 xdp_redir; /* successful XDP redirects */
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u64 xdp_err; /* packets dropped due to XDP errors */
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};
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struct funeth_rxbuf { /* per Rx buffer state */
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struct page *page; /* associated page */
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dma_addr_t dma_addr; /* DMA address of page start */
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int pg_refs; /* page refs held by driver */
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int node; /* page node, or -1 if it is PF_MEMALLOC */
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};
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struct funeth_rx_cache { /* cache of DMA-mapped previously used buffers */
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struct funeth_rxbuf *bufs; /* base of Rx buffer state ring */
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unsigned int prod_cnt; /* producer counter */
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unsigned int cons_cnt; /* consumer counter */
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unsigned int mask; /* depth - 1 */
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};
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/* An Rx queue consists of a CQ and an SQ used to provide Rx buffers. */
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struct funeth_rxq {
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struct net_device *netdev;
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struct napi_struct *napi;
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struct device *dma_dev; /* device for DMA mappings */
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void *cqes; /* base of CQ descriptor ring */
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const void *next_cqe_info; /* fun_cqe_info of next CQE */
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u32 __iomem *cq_db; /* CQ doorbell register address */
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unsigned int cq_head; /* CQ head index */
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unsigned int cq_mask; /* CQ depth - 1 */
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u16 phase; /* CQ phase tag */
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u16 qidx; /* queue index within net_device */
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unsigned int irq_db_val; /* IRQ info for CQ doorbell */
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struct fun_eprq_rqbuf *rqes; /* base of RQ descriptor ring */
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struct funeth_rxbuf *bufs; /* base of Rx buffer state ring */
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struct funeth_rxbuf *cur_buf; /* currently active buffer */
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u32 __iomem *rq_db; /* RQ doorbell register address */
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unsigned int rq_cons; /* RQ consumer counter */
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unsigned int rq_mask; /* RQ depth - 1 */
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unsigned int buf_offset; /* offset of next pkt in head buffer */
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u8 xdp_flush; /* XDP flush types needed at NAPI end */
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u8 init_state; /* queue initialization state */
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u16 headroom; /* per packet headroom */
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unsigned int rq_cons_db; /* value of rq_cons at last RQ db */
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unsigned int rq_db_thres; /* # of new buffers needed to write RQ db */
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struct funeth_rxbuf spare_buf; /* spare for next buffer replacement */
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struct funeth_rx_cache cache; /* used buffer cache */
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struct bpf_prog *xdp_prog; /* optional XDP BPF program */
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struct funeth_rxq_stats stats;
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dma_addr_t cq_dma_addr; /* DMA address of CQE ring */
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dma_addr_t rq_dma_addr; /* DMA address of RQE ring */
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u16 irq_cnt;
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u32 hw_cqid; /* device ID of the queue's CQ */
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u32 hw_sqid; /* device ID of the queue's SQ */
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int numa_node;
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struct u64_stats_sync syncp;
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struct xdp_rxq_info xdp_rxq;
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};
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#define FUN_QSTAT_INC(q, counter) \
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do { \
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u64_stats_update_begin(&(q)->syncp); \
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(q)->stats.counter++; \
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u64_stats_update_end(&(q)->syncp); \
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} while (0)
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#define FUN_QSTAT_READ(q, seq, stats_copy) \
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do { \
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seq = u64_stats_fetch_begin(&(q)->syncp); \
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stats_copy = (q)->stats; \
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} while (u64_stats_fetch_retry(&(q)->syncp, (seq)))
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#define FUN_INT_NAME_LEN (IFNAMSIZ + 16)
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struct fun_irq {
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struct napi_struct napi;
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struct funeth_txq *txq;
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struct funeth_rxq *rxq;
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u8 state;
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u16 irq_idx; /* index of MSI-X interrupt */
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int irq; /* Linux IRQ vector */
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cpumask_t affinity_mask; /* IRQ affinity */
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struct irq_affinity_notify aff_notify;
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char name[FUN_INT_NAME_LEN];
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} ____cacheline_internodealigned_in_smp;
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/* Return the start address of the idx-th Tx descriptor. */
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static inline void *fun_tx_desc_addr(const struct funeth_txq *q,
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unsigned int idx)
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{
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return q->desc + idx * FUNETH_SQE_SIZE;
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}
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static inline void fun_txq_wr_db(const struct funeth_txq *q)
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{
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unsigned int tail = q->prod_cnt & q->mask;
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writel(tail, q->db);
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}
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static inline int fun_irq_node(const struct fun_irq *p)
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{
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return cpu_to_mem(cpumask_first(&p->affinity_mask));
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}
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int fun_rxq_napi_poll(struct napi_struct *napi, int budget);
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int fun_txq_napi_poll(struct napi_struct *napi, int budget);
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netdev_tx_t fun_start_xmit(struct sk_buff *skb, struct net_device *netdev);
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bool fun_xdp_tx(struct funeth_txq *q, void *data, unsigned int len);
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int fun_xdp_xmit_frames(struct net_device *dev, int n,
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struct xdp_frame **frames, u32 flags);
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int funeth_txq_create(struct net_device *dev, unsigned int qidx,
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unsigned int ndesc, struct fun_irq *irq, int state,
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struct funeth_txq **qp);
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int fun_txq_create_dev(struct funeth_txq *q, struct fun_irq *irq);
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struct funeth_txq *funeth_txq_free(struct funeth_txq *q, int state);
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int funeth_rxq_create(struct net_device *dev, unsigned int qidx,
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unsigned int ncqe, unsigned int nrqe, struct fun_irq *irq,
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int state, struct funeth_rxq **qp);
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int fun_rxq_create_dev(struct funeth_rxq *q, struct fun_irq *irq);
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struct funeth_rxq *funeth_rxq_free(struct funeth_rxq *q, int state);
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int fun_rxq_set_bpf(struct funeth_rxq *q, struct bpf_prog *prog);
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#endif /* _FUNETH_TXRX_H */
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