513 lines
15 KiB
C
513 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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//
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// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
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//
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// Copyright (c) 2019, 2020, 2021 Pengutronix,
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// Marc Kleine-Budde <kernel@pengutronix.de>
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//
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// Based on:
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//
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// CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
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//
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// Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
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//
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#include <asm/unaligned.h>
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#include "mcp251xfd.h"
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#include "mcp251xfd-ram.h"
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static inline u8
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mcp251xfd_cmd_prepare_write_reg(const struct mcp251xfd_priv *priv,
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union mcp251xfd_write_reg_buf *write_reg_buf,
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const u16 reg, const u32 mask, const u32 val)
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{
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u8 first_byte, last_byte, len;
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u8 *data;
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__le32 val_le32;
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first_byte = mcp251xfd_first_byte_set(mask);
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last_byte = mcp251xfd_last_byte_set(mask);
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len = last_byte - first_byte + 1;
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data = mcp251xfd_spi_cmd_write(priv, write_reg_buf, reg + first_byte);
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val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
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memcpy(data, &val_le32, len);
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if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) {
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u16 crc;
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mcp251xfd_spi_cmd_crc_set_len_in_reg(&write_reg_buf->crc.cmd,
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len);
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/* CRC */
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len += sizeof(write_reg_buf->crc.cmd);
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crc = mcp251xfd_crc16_compute(&write_reg_buf->crc, len);
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put_unaligned_be16(crc, (void *)write_reg_buf + len);
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/* Total length */
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len += sizeof(write_reg_buf->crc.crc);
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} else {
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len += sizeof(write_reg_buf->nocrc.cmd);
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}
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return len;
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}
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static void
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mcp251xfd_ring_init_tef(struct mcp251xfd_priv *priv, u16 *base)
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{
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struct mcp251xfd_tef_ring *tef_ring;
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struct spi_transfer *xfer;
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u32 val;
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u16 addr;
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u8 len;
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int i;
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/* TEF */
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tef_ring = priv->tef;
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tef_ring->head = 0;
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tef_ring->tail = 0;
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/* TEF- and TX-FIFO have same number of objects */
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*base = mcp251xfd_get_tef_obj_addr(priv->tx->obj_num);
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/* FIFO IRQ enable */
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addr = MCP251XFD_REG_TEFCON;
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val = MCP251XFD_REG_TEFCON_TEFOVIE | MCP251XFD_REG_TEFCON_TEFNEIE;
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len = mcp251xfd_cmd_prepare_write_reg(priv, &tef_ring->irq_enable_buf,
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addr, val, val);
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tef_ring->irq_enable_xfer.tx_buf = &tef_ring->irq_enable_buf;
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tef_ring->irq_enable_xfer.len = len;
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spi_message_init_with_transfers(&tef_ring->irq_enable_msg,
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&tef_ring->irq_enable_xfer, 1);
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/* FIFO increment TEF tail pointer */
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addr = MCP251XFD_REG_TEFCON;
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val = MCP251XFD_REG_TEFCON_UINC;
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len = mcp251xfd_cmd_prepare_write_reg(priv, &tef_ring->uinc_buf,
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addr, val, val);
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for (i = 0; i < ARRAY_SIZE(tef_ring->uinc_xfer); i++) {
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xfer = &tef_ring->uinc_xfer[i];
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xfer->tx_buf = &tef_ring->uinc_buf;
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xfer->len = len;
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xfer->cs_change = 1;
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xfer->cs_change_delay.value = 0;
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xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
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}
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/* "cs_change == 1" on the last transfer results in an active
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* chip select after the complete SPI message. This causes the
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* controller to interpret the next register access as
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* data. Set "cs_change" of the last transfer to "0" to
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* properly deactivate the chip select at the end of the
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* message.
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*/
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xfer->cs_change = 0;
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if (priv->tx_coalesce_usecs_irq || priv->tx_obj_num_coalesce_irq) {
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val = MCP251XFD_REG_TEFCON_UINC |
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MCP251XFD_REG_TEFCON_TEFOVIE |
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MCP251XFD_REG_TEFCON_TEFHIE;
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len = mcp251xfd_cmd_prepare_write_reg(priv,
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&tef_ring->uinc_irq_disable_buf,
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addr, val, val);
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xfer->tx_buf = &tef_ring->uinc_irq_disable_buf;
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xfer->len = len;
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}
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}
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static void
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mcp251xfd_tx_ring_init_tx_obj(const struct mcp251xfd_priv *priv,
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const struct mcp251xfd_tx_ring *ring,
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struct mcp251xfd_tx_obj *tx_obj,
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const u8 rts_buf_len,
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const u8 n)
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{
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struct spi_transfer *xfer;
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u16 addr;
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/* FIFO load */
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addr = mcp251xfd_get_tx_obj_addr(ring, n);
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if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX)
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mcp251xfd_spi_cmd_write_crc_set_addr(&tx_obj->buf.crc.cmd,
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addr);
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else
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mcp251xfd_spi_cmd_write_nocrc(&tx_obj->buf.nocrc.cmd,
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addr);
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xfer = &tx_obj->xfer[0];
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xfer->tx_buf = &tx_obj->buf;
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xfer->len = 0; /* actual len is assigned on the fly */
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xfer->cs_change = 1;
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xfer->cs_change_delay.value = 0;
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xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
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/* FIFO request to send */
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xfer = &tx_obj->xfer[1];
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xfer->tx_buf = &ring->rts_buf;
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xfer->len = rts_buf_len;
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/* SPI message */
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spi_message_init_with_transfers(&tx_obj->msg, tx_obj->xfer,
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ARRAY_SIZE(tx_obj->xfer));
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}
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static void
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mcp251xfd_ring_init_tx(struct mcp251xfd_priv *priv, u16 *base, u8 *fifo_nr)
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{
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struct mcp251xfd_tx_ring *tx_ring;
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struct mcp251xfd_tx_obj *tx_obj;
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u32 val;
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u16 addr;
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u8 len;
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int i;
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tx_ring = priv->tx;
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tx_ring->head = 0;
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tx_ring->tail = 0;
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tx_ring->base = *base;
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tx_ring->nr = 0;
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tx_ring->fifo_nr = *fifo_nr;
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*base = mcp251xfd_get_tx_obj_addr(tx_ring, tx_ring->obj_num);
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*fifo_nr += 1;
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/* FIFO request to send */
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addr = MCP251XFD_REG_FIFOCON(tx_ring->fifo_nr);
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val = MCP251XFD_REG_FIFOCON_TXREQ | MCP251XFD_REG_FIFOCON_UINC;
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len = mcp251xfd_cmd_prepare_write_reg(priv, &tx_ring->rts_buf,
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addr, val, val);
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mcp251xfd_for_each_tx_obj(tx_ring, tx_obj, i)
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mcp251xfd_tx_ring_init_tx_obj(priv, tx_ring, tx_obj, len, i);
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}
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static void
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mcp251xfd_ring_init_rx(struct mcp251xfd_priv *priv, u16 *base, u8 *fifo_nr)
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{
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struct mcp251xfd_rx_ring *rx_ring;
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struct spi_transfer *xfer;
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u32 val;
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u16 addr;
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u8 len;
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int i, j;
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mcp251xfd_for_each_rx_ring(priv, rx_ring, i) {
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rx_ring->head = 0;
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rx_ring->tail = 0;
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rx_ring->base = *base;
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rx_ring->nr = i;
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rx_ring->fifo_nr = *fifo_nr;
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*base = mcp251xfd_get_rx_obj_addr(rx_ring, rx_ring->obj_num);
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*fifo_nr += 1;
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/* FIFO IRQ enable */
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addr = MCP251XFD_REG_FIFOCON(rx_ring->fifo_nr);
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val = MCP251XFD_REG_FIFOCON_RXOVIE |
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MCP251XFD_REG_FIFOCON_TFNRFNIE;
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len = mcp251xfd_cmd_prepare_write_reg(priv, &rx_ring->irq_enable_buf,
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addr, val, val);
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rx_ring->irq_enable_xfer.tx_buf = &rx_ring->irq_enable_buf;
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rx_ring->irq_enable_xfer.len = len;
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spi_message_init_with_transfers(&rx_ring->irq_enable_msg,
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&rx_ring->irq_enable_xfer, 1);
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/* FIFO increment RX tail pointer */
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val = MCP251XFD_REG_FIFOCON_UINC;
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len = mcp251xfd_cmd_prepare_write_reg(priv, &rx_ring->uinc_buf,
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addr, val, val);
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for (j = 0; j < ARRAY_SIZE(rx_ring->uinc_xfer); j++) {
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xfer = &rx_ring->uinc_xfer[j];
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xfer->tx_buf = &rx_ring->uinc_buf;
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xfer->len = len;
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xfer->cs_change = 1;
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xfer->cs_change_delay.value = 0;
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xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
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}
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/* "cs_change == 1" on the last transfer results in an
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* active chip select after the complete SPI
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* message. This causes the controller to interpret
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* the next register access as data. Set "cs_change"
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* of the last transfer to "0" to properly deactivate
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* the chip select at the end of the message.
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*/
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xfer->cs_change = 0;
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/* Use 1st RX-FIFO for IRQ coalescing. If enabled
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* (rx_coalesce_usecs_irq or rx_max_coalesce_frames_irq
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* is activated), use the last transfer to disable:
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*
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* - TFNRFNIE (Receive FIFO Not Empty Interrupt)
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*
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* and enable:
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*
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* - TFHRFHIE (Receive FIFO Half Full Interrupt)
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* - or -
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* - TFERFFIE (Receive FIFO Full Interrupt)
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*
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* depending on rx_max_coalesce_frames_irq.
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*
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* The RXOVIE (Overflow Interrupt) is always enabled.
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*/
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if (rx_ring->nr == 0 && (priv->rx_coalesce_usecs_irq ||
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priv->rx_obj_num_coalesce_irq)) {
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val = MCP251XFD_REG_FIFOCON_UINC |
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MCP251XFD_REG_FIFOCON_RXOVIE;
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if (priv->rx_obj_num_coalesce_irq == rx_ring->obj_num)
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val |= MCP251XFD_REG_FIFOCON_TFERFFIE;
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else if (priv->rx_obj_num_coalesce_irq)
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val |= MCP251XFD_REG_FIFOCON_TFHRFHIE;
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len = mcp251xfd_cmd_prepare_write_reg(priv,
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&rx_ring->uinc_irq_disable_buf,
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addr, val, val);
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xfer->tx_buf = &rx_ring->uinc_irq_disable_buf;
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xfer->len = len;
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}
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}
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}
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int mcp251xfd_ring_init(struct mcp251xfd_priv *priv)
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{
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const struct mcp251xfd_rx_ring *rx_ring;
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u16 base = 0, ram_used;
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u8 fifo_nr = 1;
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int i;
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netdev_reset_queue(priv->ndev);
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mcp251xfd_ring_init_tef(priv, &base);
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mcp251xfd_ring_init_rx(priv, &base, &fifo_nr);
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mcp251xfd_ring_init_tx(priv, &base, &fifo_nr);
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/* mcp251xfd_handle_rxif() will iterate over all RX rings.
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* Rings with their corresponding bit set in
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* priv->regs_status.rxif are read out.
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*
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* If the chip is configured for only 1 RX-FIFO, and if there
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* is an RX interrupt pending (RXIF in INT register is set),
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* it must be the 1st RX-FIFO.
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*
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* We mark the RXIF of the 1st FIFO as pending here, so that
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* we can skip the read of the RXIF register in
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* mcp251xfd_read_regs_status() for the 1 RX-FIFO only case.
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*
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* If we use more than 1 RX-FIFO, this value gets overwritten
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* in mcp251xfd_read_regs_status(), so set it unconditionally
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* here.
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*/
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priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
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if (priv->tx_obj_num_coalesce_irq) {
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netdev_dbg(priv->ndev,
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"FIFO setup: TEF: 0x%03x: %2d*%zu bytes = %4zu bytes (coalesce)\n",
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mcp251xfd_get_tef_obj_addr(0),
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priv->tx_obj_num_coalesce_irq,
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sizeof(struct mcp251xfd_hw_tef_obj),
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priv->tx_obj_num_coalesce_irq *
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sizeof(struct mcp251xfd_hw_tef_obj));
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netdev_dbg(priv->ndev,
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" 0x%03x: %2d*%zu bytes = %4zu bytes\n",
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mcp251xfd_get_tef_obj_addr(priv->tx_obj_num_coalesce_irq),
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priv->tx->obj_num - priv->tx_obj_num_coalesce_irq,
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sizeof(struct mcp251xfd_hw_tef_obj),
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(priv->tx->obj_num - priv->tx_obj_num_coalesce_irq) *
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sizeof(struct mcp251xfd_hw_tef_obj));
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} else {
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netdev_dbg(priv->ndev,
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"FIFO setup: TEF: 0x%03x: %2d*%zu bytes = %4zu bytes\n",
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mcp251xfd_get_tef_obj_addr(0),
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priv->tx->obj_num, sizeof(struct mcp251xfd_hw_tef_obj),
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priv->tx->obj_num * sizeof(struct mcp251xfd_hw_tef_obj));
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}
|
||
|
|
|
||
|
|
mcp251xfd_for_each_rx_ring(priv, rx_ring, i) {
|
||
|
|
if (rx_ring->nr == 0 && priv->rx_obj_num_coalesce_irq) {
|
||
|
|
netdev_dbg(priv->ndev,
|
||
|
|
"FIFO setup: RX-%u: FIFO %u/0x%03x: %2u*%u bytes = %4u bytes (coalesce)\n",
|
||
|
|
rx_ring->nr, rx_ring->fifo_nr,
|
||
|
|
mcp251xfd_get_rx_obj_addr(rx_ring, 0),
|
||
|
|
priv->rx_obj_num_coalesce_irq, rx_ring->obj_size,
|
||
|
|
priv->rx_obj_num_coalesce_irq * rx_ring->obj_size);
|
||
|
|
|
||
|
|
if (priv->rx_obj_num_coalesce_irq == MCP251XFD_FIFO_DEPTH)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
netdev_dbg(priv->ndev,
|
||
|
|
" 0x%03x: %2u*%u bytes = %4u bytes\n",
|
||
|
|
mcp251xfd_get_rx_obj_addr(rx_ring,
|
||
|
|
priv->rx_obj_num_coalesce_irq),
|
||
|
|
rx_ring->obj_num - priv->rx_obj_num_coalesce_irq,
|
||
|
|
rx_ring->obj_size,
|
||
|
|
(rx_ring->obj_num - priv->rx_obj_num_coalesce_irq) *
|
||
|
|
rx_ring->obj_size);
|
||
|
|
} else {
|
||
|
|
netdev_dbg(priv->ndev,
|
||
|
|
"FIFO setup: RX-%u: FIFO %u/0x%03x: %2u*%u bytes = %4u bytes\n",
|
||
|
|
rx_ring->nr, rx_ring->fifo_nr,
|
||
|
|
mcp251xfd_get_rx_obj_addr(rx_ring, 0),
|
||
|
|
rx_ring->obj_num, rx_ring->obj_size,
|
||
|
|
rx_ring->obj_num * rx_ring->obj_size);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
netdev_dbg(priv->ndev,
|
||
|
|
"FIFO setup: TX: FIFO %u/0x%03x: %2u*%u bytes = %4u bytes\n",
|
||
|
|
priv->tx->fifo_nr,
|
||
|
|
mcp251xfd_get_tx_obj_addr(priv->tx, 0),
|
||
|
|
priv->tx->obj_num, priv->tx->obj_size,
|
||
|
|
priv->tx->obj_num * priv->tx->obj_size);
|
||
|
|
|
||
|
|
netdev_dbg(priv->ndev,
|
||
|
|
"FIFO setup: free: %4d bytes\n",
|
||
|
|
MCP251XFD_RAM_SIZE - (base - MCP251XFD_RAM_START));
|
||
|
|
|
||
|
|
ram_used = base - MCP251XFD_RAM_START;
|
||
|
|
if (ram_used > MCP251XFD_RAM_SIZE) {
|
||
|
|
netdev_err(priv->ndev,
|
||
|
|
"Error during ring configuration, using more RAM (%u bytes) than available (%u bytes).\n",
|
||
|
|
ram_used, MCP251XFD_RAM_SIZE);
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mcp251xfd_ring_free(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = ARRAY_SIZE(priv->rx) - 1; i >= 0; i--) {
|
||
|
|
kfree(priv->rx[i]);
|
||
|
|
priv->rx[i] = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static enum hrtimer_restart mcp251xfd_rx_irq_timer(struct hrtimer *t)
|
||
|
|
{
|
||
|
|
struct mcp251xfd_priv *priv = container_of(t, struct mcp251xfd_priv,
|
||
|
|
rx_irq_timer);
|
||
|
|
struct mcp251xfd_rx_ring *ring = priv->rx[0];
|
||
|
|
|
||
|
|
if (test_bit(MCP251XFD_FLAGS_DOWN, priv->flags))
|
||
|
|
return HRTIMER_NORESTART;
|
||
|
|
|
||
|
|
spi_async(priv->spi, &ring->irq_enable_msg);
|
||
|
|
|
||
|
|
return HRTIMER_NORESTART;
|
||
|
|
}
|
||
|
|
|
||
|
|
static enum hrtimer_restart mcp251xfd_tx_irq_timer(struct hrtimer *t)
|
||
|
|
{
|
||
|
|
struct mcp251xfd_priv *priv = container_of(t, struct mcp251xfd_priv,
|
||
|
|
tx_irq_timer);
|
||
|
|
struct mcp251xfd_tef_ring *ring = priv->tef;
|
||
|
|
|
||
|
|
if (test_bit(MCP251XFD_FLAGS_DOWN, priv->flags))
|
||
|
|
return HRTIMER_NORESTART;
|
||
|
|
|
||
|
|
spi_async(priv->spi, &ring->irq_enable_msg);
|
||
|
|
|
||
|
|
return HRTIMER_NORESTART;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct can_ram_config mcp251xfd_ram_config = {
|
||
|
|
.rx = {
|
||
|
|
.size[CAN_RAM_MODE_CAN] = sizeof(struct mcp251xfd_hw_rx_obj_can),
|
||
|
|
.size[CAN_RAM_MODE_CANFD] = sizeof(struct mcp251xfd_hw_rx_obj_canfd),
|
||
|
|
.min = MCP251XFD_RX_OBJ_NUM_MIN,
|
||
|
|
.max = MCP251XFD_RX_OBJ_NUM_MAX,
|
||
|
|
.def[CAN_RAM_MODE_CAN] = CAN_RAM_NUM_MAX,
|
||
|
|
.def[CAN_RAM_MODE_CANFD] = CAN_RAM_NUM_MAX,
|
||
|
|
.fifo_num = MCP251XFD_FIFO_RX_NUM,
|
||
|
|
.fifo_depth_min = MCP251XFD_RX_FIFO_DEPTH_MIN,
|
||
|
|
.fifo_depth_coalesce_min = MCP251XFD_RX_FIFO_DEPTH_COALESCE_MIN,
|
||
|
|
},
|
||
|
|
.tx = {
|
||
|
|
.size[CAN_RAM_MODE_CAN] = sizeof(struct mcp251xfd_hw_tef_obj) +
|
||
|
|
sizeof(struct mcp251xfd_hw_tx_obj_can),
|
||
|
|
.size[CAN_RAM_MODE_CANFD] = sizeof(struct mcp251xfd_hw_tef_obj) +
|
||
|
|
sizeof(struct mcp251xfd_hw_tx_obj_canfd),
|
||
|
|
.min = MCP251XFD_TX_OBJ_NUM_MIN,
|
||
|
|
.max = MCP251XFD_TX_OBJ_NUM_MAX,
|
||
|
|
.def[CAN_RAM_MODE_CAN] = MCP251XFD_TX_OBJ_NUM_CAN_DEFAULT,
|
||
|
|
.def[CAN_RAM_MODE_CANFD] = MCP251XFD_TX_OBJ_NUM_CANFD_DEFAULT,
|
||
|
|
.fifo_num = MCP251XFD_FIFO_TX_NUM,
|
||
|
|
.fifo_depth_min = MCP251XFD_TX_FIFO_DEPTH_MIN,
|
||
|
|
.fifo_depth_coalesce_min = MCP251XFD_TX_FIFO_DEPTH_COALESCE_MIN,
|
||
|
|
},
|
||
|
|
.size = MCP251XFD_RAM_SIZE,
|
||
|
|
.fifo_depth = MCP251XFD_FIFO_DEPTH,
|
||
|
|
};
|
||
|
|
|
||
|
|
int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
const bool fd_mode = mcp251xfd_is_fd_mode(priv);
|
||
|
|
struct mcp251xfd_tx_ring *tx_ring = priv->tx;
|
||
|
|
struct mcp251xfd_rx_ring *rx_ring;
|
||
|
|
u8 tx_obj_size, rx_obj_size;
|
||
|
|
u8 rem, i;
|
||
|
|
|
||
|
|
/* switching from CAN-2.0 to CAN-FD mode or vice versa */
|
||
|
|
if (fd_mode != test_bit(MCP251XFD_FLAGS_FD_MODE, priv->flags)) {
|
||
|
|
struct can_ram_layout layout;
|
||
|
|
|
||
|
|
can_ram_get_layout(&layout, &mcp251xfd_ram_config, NULL, NULL, fd_mode);
|
||
|
|
priv->rx_obj_num = layout.default_rx;
|
||
|
|
tx_ring->obj_num = layout.default_tx;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (fd_mode) {
|
||
|
|
tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_canfd);
|
||
|
|
rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_canfd);
|
||
|
|
set_bit(MCP251XFD_FLAGS_FD_MODE, priv->flags);
|
||
|
|
} else {
|
||
|
|
tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_can);
|
||
|
|
rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_can);
|
||
|
|
clear_bit(MCP251XFD_FLAGS_FD_MODE, priv->flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
tx_ring->obj_size = tx_obj_size;
|
||
|
|
|
||
|
|
rem = priv->rx_obj_num;
|
||
|
|
for (i = 0; i < ARRAY_SIZE(priv->rx) && rem; i++) {
|
||
|
|
u8 rx_obj_num;
|
||
|
|
|
||
|
|
if (i == 0 && priv->rx_obj_num_coalesce_irq)
|
||
|
|
rx_obj_num = min_t(u8, priv->rx_obj_num_coalesce_irq * 2,
|
||
|
|
MCP251XFD_FIFO_DEPTH);
|
||
|
|
else
|
||
|
|
rx_obj_num = min_t(u8, rounddown_pow_of_two(rem),
|
||
|
|
MCP251XFD_FIFO_DEPTH);
|
||
|
|
rem -= rx_obj_num;
|
||
|
|
|
||
|
|
rx_ring = kzalloc(sizeof(*rx_ring) + rx_obj_size * rx_obj_num,
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!rx_ring) {
|
||
|
|
mcp251xfd_ring_free(priv);
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
rx_ring->obj_num = rx_obj_num;
|
||
|
|
rx_ring->obj_size = rx_obj_size;
|
||
|
|
priv->rx[i] = rx_ring;
|
||
|
|
}
|
||
|
|
priv->rx_ring_num = i;
|
||
|
|
|
||
|
|
hrtimer_init(&priv->rx_irq_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||
|
|
priv->rx_irq_timer.function = mcp251xfd_rx_irq_timer;
|
||
|
|
|
||
|
|
hrtimer_init(&priv->tx_irq_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||
|
|
priv->tx_irq_timer.function = mcp251xfd_tx_irq_timer;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|