338 lines
8.4 KiB
C
338 lines
8.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
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*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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#include <linux/io.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include "sdhci-pltfm.h"
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#include "cqhci.h"
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#define SDHCI_VENDOR 0x78
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#define SDHCI_VENDOR_ENHANCED_STRB 0x1
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#define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0)
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#define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1)
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#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
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struct sdhci_brcmstb_priv {
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void __iomem *cfg_regs;
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bool has_cqe;
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};
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struct brcmstb_match_priv {
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void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
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struct sdhci_ops *ops;
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unsigned int flags;
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};
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static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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u32 reg;
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dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
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__func__);
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reg = readl(host->ioaddr + SDHCI_VENDOR);
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if (ios->enhanced_strobe)
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reg |= SDHCI_VENDOR_ENHANCED_STRB;
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else
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reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
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writel(reg, host->ioaddr + SDHCI_VENDOR);
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}
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static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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host->mmc->actual_clock = 0;
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clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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sdhci_enable_clk(host, clk);
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}
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static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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u16 ctrl_2;
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dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
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__func__, timing);
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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if ((timing == MMC_TIMING_MMC_HS200) ||
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(timing == MMC_TIMING_UHS_SDR104))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (timing == MMC_TIMING_UHS_SDR12)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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else if (timing == MMC_TIMING_SD_HS ||
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timing == MMC_TIMING_MMC_HS ||
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timing == MMC_TIMING_UHS_SDR25)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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else if ((timing == MMC_TIMING_UHS_DDR50) ||
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(timing == MMC_TIMING_MMC_DDR52))
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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else if (timing == MMC_TIMING_MMC_HS400)
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ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
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{
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sdhci_dumpregs(mmc_priv(mmc));
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}
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static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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u32 reg;
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reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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while (reg & SDHCI_DATA_AVAILABLE) {
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sdhci_readl(host, SDHCI_BUFFER);
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reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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}
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sdhci_cqe_enable(mmc);
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}
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static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
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.enable = sdhci_brcmstb_cqe_enable,
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.disable = sdhci_cqe_disable,
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.dumpregs = sdhci_brcmstb_dumpregs,
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};
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static struct sdhci_ops sdhci_brcmstb_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
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.set_clock = sdhci_brcmstb_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
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};
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static struct brcmstb_match_priv match_priv_7425 = {
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.flags = BRCMSTB_PRIV_FLAGS_NO_64BIT |
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BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
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.ops = &sdhci_brcmstb_ops,
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};
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static struct brcmstb_match_priv match_priv_7445 = {
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.flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
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.ops = &sdhci_brcmstb_ops,
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};
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static const struct brcmstb_match_priv match_priv_7216 = {
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.hs400es = sdhci_brcmstb_hs400es,
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.ops = &sdhci_brcmstb_ops_7216,
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};
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static const struct of_device_id sdhci_brcm_of_match[] = {
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{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
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{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
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{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
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{},
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};
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static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
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{
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int cmd_error = 0;
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int data_error = 0;
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if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
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return intmask;
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cqhci_irq(host->mmc, intmask, cmd_error, data_error);
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return 0;
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}
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static int sdhci_brcmstb_add_host(struct sdhci_host *host,
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struct sdhci_brcmstb_priv *priv)
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{
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struct cqhci_host *cq_host;
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bool dma64;
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int ret;
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if (!priv->has_cqe)
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return sdhci_add_host(host);
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dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
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host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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ret = sdhci_setup_host(host);
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if (ret)
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return ret;
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cq_host = devm_kzalloc(mmc_dev(host->mmc),
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sizeof(*cq_host), GFP_KERNEL);
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if (!cq_host) {
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ret = -ENOMEM;
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goto cleanup;
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}
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cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
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cq_host->ops = &sdhci_brcmstb_cqhci_ops;
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dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
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if (dma64) {
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dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
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cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
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}
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ret = cqhci_init(cq_host, host->mmc, dma64);
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if (ret)
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goto cleanup;
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ret = __sdhci_add_host(host);
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if (ret)
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goto cleanup;
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return 0;
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cleanup:
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sdhci_cleanup_host(host);
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return ret;
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}
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static int sdhci_brcmstb_probe(struct platform_device *pdev)
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{
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const struct brcmstb_match_priv *match_priv;
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struct sdhci_pltfm_data brcmstb_pdata;
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struct sdhci_pltfm_host *pltfm_host;
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const struct of_device_id *match;
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struct sdhci_brcmstb_priv *priv;
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struct sdhci_host *host;
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struct resource *iomem;
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bool has_cqe = false;
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struct clk *clk;
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int res;
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match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
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match_priv = match->data;
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dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible);
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clk = devm_clk_get_optional(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(clk),
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"Failed to get clock from Device Tree\n");
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res = clk_prepare_enable(clk);
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if (res)
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return res;
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memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
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if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
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has_cqe = true;
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match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
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}
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brcmstb_pdata.ops = match_priv->ops;
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host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
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sizeof(struct sdhci_brcmstb_priv));
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if (IS_ERR(host)) {
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res = PTR_ERR(host);
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goto err_clk;
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}
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pltfm_host = sdhci_priv(host);
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priv = sdhci_pltfm_priv(pltfm_host);
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priv->has_cqe = has_cqe;
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/* Map in the non-standard CFG registers */
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
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if (IS_ERR(priv->cfg_regs)) {
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res = PTR_ERR(priv->cfg_regs);
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goto err;
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}
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sdhci_get_of_property(pdev);
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res = mmc_of_parse(host->mmc);
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if (res)
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goto err;
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/*
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* If the chip has enhanced strobe and it's enabled, add
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* callback
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*/
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if (match_priv->hs400es &&
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(host->mmc->caps2 & MMC_CAP2_HS400_ES))
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host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
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/*
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* Supply the existing CAPS, but clear the UHS modes. This
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* will allow these modes to be specified by device tree
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* properties through mmc_of_parse().
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*/
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host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT)
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host->caps &= ~SDHCI_CAN_64BIT;
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host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
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host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
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SDHCI_SUPPORT_DDR50);
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host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
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if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT)
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host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
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res = sdhci_brcmstb_add_host(host, priv);
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if (res)
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goto err;
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pltfm_host->clk = clk;
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return res;
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err:
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sdhci_pltfm_free(pdev);
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err_clk:
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clk_disable_unprepare(clk);
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return res;
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}
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static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
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{
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sdhci_pltfm_suspend(&pdev->dev);
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}
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MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
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static struct platform_driver sdhci_brcmstb_driver = {
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.driver = {
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.name = "sdhci-brcmstb",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.pm = &sdhci_pltfm_pmops,
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.of_match_table = of_match_ptr(sdhci_brcm_of_match),
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},
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.probe = sdhci_brcmstb_probe,
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.remove = sdhci_pltfm_unregister,
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.shutdown = sdhci_brcmstb_shutdown,
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};
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module_platform_driver(sdhci_brcmstb_driver);
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MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
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MODULE_AUTHOR("Broadcom");
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MODULE_LICENSE("GPL v2");
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