526 lines
13 KiB
C
526 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for most of the SPI EEPROMs, such as Atmel AT25 models
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* and Cypress FRAMs FM25 models.
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*
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* Copyright (C) 2006 David Brownell
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*/
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/spi/eeprom.h>
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#include <linux/spi/spi.h>
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#include <linux/nvmem-provider.h>
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/*
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* NOTE: this is an *EEPROM* driver. The vagaries of product naming
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* mean that some AT25 products are EEPROMs, and others are FLASH.
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* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
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* not this one!
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*
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* EEPROMs that can be used with this driver include, for example:
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* AT25M02, AT25128B
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*/
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#define FM25_SN_LEN 8 /* serial number length */
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#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
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struct at25_data {
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struct spi_eeprom chip;
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struct spi_device *spi;
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struct mutex lock;
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unsigned addrlen;
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struct nvmem_config nvmem_config;
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struct nvmem_device *nvmem;
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u8 sernum[FM25_SN_LEN];
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u8 command[EE_MAXADDRLEN + 1];
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};
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#define AT25_WREN 0x06 /* latch the write enable */
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#define AT25_WRDI 0x04 /* reset the write enable */
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#define AT25_RDSR 0x05 /* read status register */
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#define AT25_WRSR 0x01 /* write status register */
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#define AT25_READ 0x03 /* read byte(s) */
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#define AT25_WRITE 0x02 /* write byte(s)/sector */
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#define FM25_SLEEP 0xb9 /* enter sleep mode */
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#define FM25_RDID 0x9f /* read device ID */
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#define FM25_RDSN 0xc3 /* read S/N */
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#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
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#define AT25_SR_WEN 0x02 /* write enable (latched) */
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#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
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#define AT25_SR_BP1 0x08
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#define AT25_SR_WPEN 0x80 /* writeprotect enable */
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#define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */
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#define FM25_ID_LEN 9 /* ID length */
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/*
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* Specs often allow 5ms for a page write, sometimes 20ms;
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* it's important to recover from write timeouts.
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*/
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#define EE_TIMEOUT 25
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/*-------------------------------------------------------------------------*/
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#define io_limit PAGE_SIZE /* bytes */
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static int at25_ee_read(void *priv, unsigned int offset,
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void *val, size_t count)
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{
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struct at25_data *at25 = priv;
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char *buf = val;
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u8 *cp;
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ssize_t status;
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struct spi_transfer t[2];
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struct spi_message m;
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u8 instr;
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if (unlikely(offset >= at25->chip.byte_len))
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return -EINVAL;
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if ((offset + count) > at25->chip.byte_len)
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count = at25->chip.byte_len - offset;
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if (unlikely(!count))
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return -EINVAL;
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cp = at25->command;
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instr = AT25_READ;
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if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
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if (offset >= BIT(at25->addrlen * 8))
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instr |= AT25_INSTR_BIT3;
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mutex_lock(&at25->lock);
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*cp++ = instr;
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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fallthrough;
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case 2:
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*cp++ = offset >> 8;
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fallthrough;
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case 1:
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case 0: /* can't happen: for better code generation */
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*cp++ = offset >> 0;
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}
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = at25->command;
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t[0].len = at25->addrlen + 1;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = count;
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spi_message_add_tail(&t[1], &m);
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/*
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* Read it all at once.
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*
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* REVISIT that's potentially a problem with large chips, if
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* other devices on the bus need to be accessed regularly or
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* this chip is clocked very slowly.
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*/
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status = spi_sync(at25->spi, &m);
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dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
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count, offset, status);
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mutex_unlock(&at25->lock);
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return status;
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}
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/* Read extra registers as ID or serial number */
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static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
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int len)
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{
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int status;
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struct spi_transfer t[2];
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struct spi_message m;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = at25->command;
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t[0].len = 1;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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mutex_lock(&at25->lock);
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at25->command[0] = command;
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status = spi_sync(at25->spi, &m);
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dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);
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mutex_unlock(&at25->lock);
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return status;
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}
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static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct at25_data *at25;
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at25 = dev_get_drvdata(dev);
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return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
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}
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static DEVICE_ATTR_RO(sernum);
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static struct attribute *sernum_attrs[] = {
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&dev_attr_sernum.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(sernum);
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static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
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{
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struct at25_data *at25 = priv;
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const char *buf = val;
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int status = 0;
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unsigned buf_size;
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u8 *bounce;
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if (unlikely(off >= at25->chip.byte_len))
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return -EFBIG;
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if ((off + count) > at25->chip.byte_len)
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count = at25->chip.byte_len - off;
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if (unlikely(!count))
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return -EINVAL;
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/* Temp buffer starts with command and address */
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buf_size = at25->chip.page_size;
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if (buf_size > io_limit)
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buf_size = io_limit;
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bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
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if (!bounce)
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return -ENOMEM;
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/*
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* For write, rollover is within the page ... so we write at
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* most one page, then manually roll over to the next page.
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*/
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mutex_lock(&at25->lock);
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do {
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unsigned long timeout, retries;
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unsigned segment;
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unsigned offset = (unsigned) off;
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u8 *cp = bounce;
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int sr;
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u8 instr;
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*cp = AT25_WREN;
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status = spi_write(at25->spi, cp, 1);
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if (status < 0) {
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dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
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break;
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}
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instr = AT25_WRITE;
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if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
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if (offset >= BIT(at25->addrlen * 8))
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instr |= AT25_INSTR_BIT3;
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*cp++ = instr;
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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fallthrough;
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case 2:
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*cp++ = offset >> 8;
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fallthrough;
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case 1:
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case 0: /* can't happen: for better code generation */
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*cp++ = offset >> 0;
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}
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/* Write as much of a page as we can */
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segment = buf_size - (offset % buf_size);
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if (segment > count)
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segment = count;
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memcpy(cp, buf, segment);
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status = spi_write(at25->spi, bounce,
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segment + at25->addrlen + 1);
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dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
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segment, offset, status);
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if (status < 0)
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break;
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/*
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* REVISIT this should detect (or prevent) failed writes
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* to read-only sections of the EEPROM...
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*/
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/* Wait for non-busy status */
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timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
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retries = 0;
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do {
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sr = spi_w8r8(at25->spi, AT25_RDSR);
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if (sr < 0 || (sr & AT25_SR_nRDY)) {
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dev_dbg(&at25->spi->dev,
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"rdsr --> %d (%02x)\n", sr, sr);
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/* at HZ=100, this is sloooow */
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msleep(1);
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continue;
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}
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if (!(sr & AT25_SR_nRDY))
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break;
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} while (retries++ < 3 || time_before_eq(jiffies, timeout));
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if ((sr < 0) || (sr & AT25_SR_nRDY)) {
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dev_err(&at25->spi->dev,
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"write %u bytes offset %u, timeout after %u msecs\n",
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segment, offset,
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jiffies_to_msecs(jiffies -
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(timeout - EE_TIMEOUT)));
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status = -ETIMEDOUT;
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break;
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}
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off += segment;
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buf += segment;
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count -= segment;
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} while (count > 0);
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mutex_unlock(&at25->lock);
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kfree(bounce);
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return status;
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}
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/*-------------------------------------------------------------------------*/
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static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
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{
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u32 val;
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int err;
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strscpy(chip->name, "at25", sizeof(chip->name));
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err = device_property_read_u32(dev, "size", &val);
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if (err)
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err = device_property_read_u32(dev, "at25,byte-len", &val);
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if (err) {
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dev_err(dev, "Error: missing \"size\" property\n");
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return err;
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}
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chip->byte_len = val;
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err = device_property_read_u32(dev, "pagesize", &val);
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if (err)
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err = device_property_read_u32(dev, "at25,page-size", &val);
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if (err) {
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dev_err(dev, "Error: missing \"pagesize\" property\n");
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return err;
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}
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chip->page_size = val;
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err = device_property_read_u32(dev, "address-width", &val);
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if (err) {
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err = device_property_read_u32(dev, "at25,addr-mode", &val);
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if (err) {
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dev_err(dev, "Error: missing \"address-width\" property\n");
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return err;
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}
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chip->flags = (u16)val;
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} else {
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switch (val) {
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case 9:
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chip->flags |= EE_INSTR_BIT3_IS_ADDR;
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fallthrough;
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case 8:
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chip->flags |= EE_ADDR1;
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break;
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case 16:
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chip->flags |= EE_ADDR2;
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break;
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case 24:
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chip->flags |= EE_ADDR3;
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break;
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default:
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dev_err(dev,
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"Error: bad \"address-width\" property: %u\n",
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val);
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return -ENODEV;
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}
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if (device_property_present(dev, "read-only"))
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chip->flags |= EE_READONLY;
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}
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return 0;
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}
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static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip)
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{
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struct at25_data *at25 = container_of(chip, struct at25_data, chip);
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u8 sernum[FM25_SN_LEN];
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u8 id[FM25_ID_LEN];
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int i;
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strscpy(chip->name, "fm25", sizeof(chip->name));
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/* Get ID of chip */
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fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
|
||
|
|
if (id[6] != 0xc2) {
|
||
|
|
dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]);
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
/* Set size found in ID */
|
||
|
|
if (id[7] < 0x21 || id[7] > 0x26) {
|
||
|
|
dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
|
||
|
|
if (chip->byte_len > 64 * 1024)
|
||
|
|
chip->flags |= EE_ADDR3;
|
||
|
|
else
|
||
|
|
chip->flags |= EE_ADDR2;
|
||
|
|
|
||
|
|
if (id[8]) {
|
||
|
|
fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
|
||
|
|
/* Swap byte order */
|
||
|
|
for (i = 0; i < FM25_SN_LEN; i++)
|
||
|
|
at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
|
||
|
|
}
|
||
|
|
|
||
|
|
chip->page_size = PAGE_SIZE;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id at25_of_match[] = {
|
||
|
|
{ .compatible = "atmel,at25" },
|
||
|
|
{ .compatible = "cypress,fm25" },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, at25_of_match);
|
||
|
|
|
||
|
|
static const struct spi_device_id at25_spi_ids[] = {
|
||
|
|
{ .name = "at25" },
|
||
|
|
{ .name = "fm25" },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(spi, at25_spi_ids);
|
||
|
|
|
||
|
|
static int at25_probe(struct spi_device *spi)
|
||
|
|
{
|
||
|
|
struct at25_data *at25 = NULL;
|
||
|
|
int err;
|
||
|
|
int sr;
|
||
|
|
struct spi_eeprom *pdata;
|
||
|
|
bool is_fram;
|
||
|
|
|
||
|
|
err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
|
||
|
|
if (err >= 0)
|
||
|
|
is_fram = true;
|
||
|
|
else
|
||
|
|
is_fram = false;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Ping the chip ... the status register is pretty portable,
|
||
|
|
* unlike probing manufacturer IDs. We do expect that system
|
||
|
|
* firmware didn't write it in the past few milliseconds!
|
||
|
|
*/
|
||
|
|
sr = spi_w8r8(spi, AT25_RDSR);
|
||
|
|
if (sr < 0 || sr & AT25_SR_nRDY) {
|
||
|
|
dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
|
||
|
|
return -ENXIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL);
|
||
|
|
if (!at25)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
mutex_init(&at25->lock);
|
||
|
|
at25->spi = spi;
|
||
|
|
spi_set_drvdata(spi, at25);
|
||
|
|
|
||
|
|
/* Chip description */
|
||
|
|
pdata = dev_get_platdata(&spi->dev);
|
||
|
|
if (pdata) {
|
||
|
|
at25->chip = *pdata;
|
||
|
|
} else {
|
||
|
|
if (is_fram)
|
||
|
|
err = at25_fram_to_chip(&spi->dev, &at25->chip);
|
||
|
|
else
|
||
|
|
err = at25_fw_to_chip(&spi->dev, &at25->chip);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* For now we only support 8/16/24 bit addressing */
|
||
|
|
if (at25->chip.flags & EE_ADDR1)
|
||
|
|
at25->addrlen = 1;
|
||
|
|
else if (at25->chip.flags & EE_ADDR2)
|
||
|
|
at25->addrlen = 2;
|
||
|
|
else if (at25->chip.flags & EE_ADDR3)
|
||
|
|
at25->addrlen = 3;
|
||
|
|
else {
|
||
|
|
dev_dbg(&spi->dev, "unsupported address type\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
|
||
|
|
at25->nvmem_config.name = dev_name(&spi->dev);
|
||
|
|
at25->nvmem_config.dev = &spi->dev;
|
||
|
|
at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
|
||
|
|
at25->nvmem_config.root_only = true;
|
||
|
|
at25->nvmem_config.owner = THIS_MODULE;
|
||
|
|
at25->nvmem_config.compat = true;
|
||
|
|
at25->nvmem_config.base_dev = &spi->dev;
|
||
|
|
at25->nvmem_config.reg_read = at25_ee_read;
|
||
|
|
at25->nvmem_config.reg_write = at25_ee_write;
|
||
|
|
at25->nvmem_config.priv = at25;
|
||
|
|
at25->nvmem_config.stride = 1;
|
||
|
|
at25->nvmem_config.word_size = 1;
|
||
|
|
at25->nvmem_config.size = at25->chip.byte_len;
|
||
|
|
|
||
|
|
at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
|
||
|
|
if (IS_ERR(at25->nvmem))
|
||
|
|
return PTR_ERR(at25->nvmem);
|
||
|
|
|
||
|
|
dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
|
||
|
|
(at25->chip.byte_len < 1024) ?
|
||
|
|
at25->chip.byte_len : (at25->chip.byte_len / 1024),
|
||
|
|
(at25->chip.byte_len < 1024) ? "Byte" : "KByte",
|
||
|
|
at25->chip.name, is_fram ? "fram" : "eeprom",
|
||
|
|
(at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
|
||
|
|
at25->chip.page_size);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
static struct spi_driver at25_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "at25",
|
||
|
|
.of_match_table = at25_of_match,
|
||
|
|
.dev_groups = sernum_groups,
|
||
|
|
},
|
||
|
|
.probe = at25_probe,
|
||
|
|
.id_table = at25_spi_ids,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_spi_driver(at25_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
|
||
|
|
MODULE_AUTHOR("David Brownell");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("spi:at25");
|