528 lines
13 KiB
C
528 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADRF6780 driver
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*
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* Copyright 2021 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/iio/iio.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/spi/spi.h>
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#include <asm/unaligned.h>
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/* ADRF6780 Register Map */
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#define ADRF6780_REG_CONTROL 0x00
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#define ADRF6780_REG_ALARM_READBACK 0x01
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#define ADRF6780_REG_ALARM_MASKS 0x02
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#define ADRF6780_REG_ENABLE 0x03
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#define ADRF6780_REG_LINEARIZE 0x04
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#define ADRF6780_REG_LO_PATH 0x05
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#define ADRF6780_REG_ADC_CONTROL 0x06
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#define ADRF6780_REG_ADC_OUTPUT 0x0C
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/* ADRF6780_REG_CONTROL Map */
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#define ADRF6780_PARITY_EN_MSK BIT(15)
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#define ADRF6780_SOFT_RESET_MSK BIT(14)
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#define ADRF6780_CHIP_ID_MSK GENMASK(11, 4)
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#define ADRF6780_CHIP_ID 0xA
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#define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0)
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/* ADRF6780_REG_ALARM_READBACK Map */
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#define ADRF6780_PARITY_ERROR_MSK BIT(15)
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#define ADRF6780_TOO_FEW_ERRORS_MSK BIT(14)
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#define ADRF6780_TOO_MANY_ERRORS_MSK BIT(13)
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#define ADRF6780_ADDRESS_RANGE_ERROR_MSK BIT(12)
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/* ADRF6780_REG_ENABLE Map */
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#define ADRF6780_VGA_BUFFER_EN_MSK BIT(8)
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#define ADRF6780_DETECTOR_EN_MSK BIT(7)
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#define ADRF6780_LO_BUFFER_EN_MSK BIT(6)
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#define ADRF6780_IF_MODE_EN_MSK BIT(5)
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#define ADRF6780_IQ_MODE_EN_MSK BIT(4)
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#define ADRF6780_LO_X2_EN_MSK BIT(3)
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#define ADRF6780_LO_PPF_EN_MSK BIT(2)
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#define ADRF6780_LO_EN_MSK BIT(1)
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#define ADRF6780_UC_BIAS_EN_MSK BIT(0)
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/* ADRF6780_REG_LINEARIZE Map */
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#define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0)
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/* ADRF6780_REG_LO_PATH Map */
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#define ADRF6780_LO_SIDEBAND_MSK BIT(10)
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#define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4)
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#define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0)
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/* ADRF6780_REG_ADC_CONTROL Map */
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#define ADRF6780_VDET_OUTPUT_SELECT_MSK BIT(3)
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#define ADRF6780_ADC_START_MSK BIT(2)
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#define ADRF6780_ADC_EN_MSK BIT(1)
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#define ADRF6780_ADC_CLOCK_EN_MSK BIT(0)
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/* ADRF6780_REG_ADC_OUTPUT Map */
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#define ADRF6780_ADC_STATUS_MSK BIT(8)
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#define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0)
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struct adrf6780_state {
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struct spi_device *spi;
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struct clk *clkin;
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/* Protect against concurrent accesses to the device */
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struct mutex lock;
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bool vga_buff_en;
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bool lo_buff_en;
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bool if_mode_en;
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bool iq_mode_en;
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bool lo_x2_en;
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bool lo_ppf_en;
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bool lo_en;
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bool uc_bias_en;
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bool lo_sideband;
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bool vdet_out_en;
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u8 data[3] ____cacheline_aligned;
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};
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static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
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unsigned int *val)
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{
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int ret;
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struct spi_transfer t = {0};
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st->data[0] = 0x80 | (reg << 1);
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st->data[1] = 0x0;
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st->data[2] = 0x0;
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t.rx_buf = &st->data[0];
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t.tx_buf = &st->data[0];
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t.len = 3;
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ret = spi_sync_transfer(st->spi, &t, 1);
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if (ret)
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return ret;
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*val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0);
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return ret;
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}
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static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
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unsigned int *val)
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{
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int ret;
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mutex_lock(&st->lock);
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ret = __adrf6780_spi_read(st, reg, val);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int __adrf6780_spi_write(struct adrf6780_state *st,
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unsigned int reg,
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unsigned int val)
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{
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put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]);
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return spi_write(st->spi, &st->data[0], 3);
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}
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static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg,
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unsigned int val)
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{
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int ret;
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mutex_lock(&st->lock);
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ret = __adrf6780_spi_write(st, reg, val);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int __adrf6780_spi_update_bits(struct adrf6780_state *st,
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unsigned int reg, unsigned int mask,
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unsigned int val)
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{
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int ret;
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unsigned int data, temp;
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ret = __adrf6780_spi_read(st, reg, &data);
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if (ret)
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return ret;
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temp = (data & ~mask) | (val & mask);
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return __adrf6780_spi_write(st, reg, temp);
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}
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static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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int ret;
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mutex_lock(&st->lock);
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ret = __adrf6780_spi_update_bits(st, reg, mask, val);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val)
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{
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int ret;
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mutex_lock(&st->lock);
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ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
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ADRF6780_ADC_EN_MSK |
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ADRF6780_ADC_CLOCK_EN_MSK |
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ADRF6780_ADC_START_MSK,
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FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) |
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FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) |
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FIELD_PREP(ADRF6780_ADC_START_MSK, 1));
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if (ret)
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goto exit;
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/* Recommended delay for the ADC to be ready*/
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usleep_range(200, 250);
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ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
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if (ret)
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goto exit;
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if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) {
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ret = -EINVAL;
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goto exit;
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}
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ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
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ADRF6780_ADC_START_MSK,
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FIELD_PREP(ADRF6780_ADC_START_MSK, 0));
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if (ret)
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goto exit;
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ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
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exit:
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mutex_unlock(&st->lock);
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return ret;
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}
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static int adrf6780_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long info)
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{
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struct adrf6780_state *dev = iio_priv(indio_dev);
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unsigned int data;
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int ret;
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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ret = adrf6780_read_adc_raw(dev, &data);
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if (ret)
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return ret;
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*val = data & ADRF6780_ADC_VALUE_MSK;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data);
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if (ret)
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return ret;
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*val = data & ADRF6780_RDAC_LINEARIZE_MSK;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_PHASE:
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ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data);
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if (ret)
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return ret;
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switch (chan->channel2) {
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case IIO_MOD_I:
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*val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK;
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return IIO_VAL_INT;
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case IIO_MOD_Q:
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*val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
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data);
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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default:
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return -EINVAL;
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}
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}
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static int adrf6780_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long info)
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{
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struct adrf6780_state *st = iio_priv(indio_dev);
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switch (info) {
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case IIO_CHAN_INFO_SCALE:
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return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val);
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case IIO_CHAN_INFO_PHASE:
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switch (chan->channel2) {
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case IIO_MOD_I:
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return adrf6780_spi_update_bits(st,
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ADRF6780_REG_LO_PATH,
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ADRF6780_I_PATH_PHASE_ACCURACY_MSK,
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FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val));
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case IIO_MOD_Q:
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return adrf6780_spi_update_bits(st,
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ADRF6780_REG_LO_PATH,
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ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
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FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val));
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default:
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return -EINVAL;
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}
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default:
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return -EINVAL;
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}
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}
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static int adrf6780_reg_access(struct iio_dev *indio_dev,
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unsigned int reg,
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unsigned int write_val,
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unsigned int *read_val)
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{
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struct adrf6780_state *st = iio_priv(indio_dev);
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if (read_val)
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return adrf6780_spi_read(st, reg, read_val);
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else
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return adrf6780_spi_write(st, reg, write_val);
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}
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static const struct iio_info adrf6780_info = {
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.read_raw = adrf6780_read_raw,
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.write_raw = adrf6780_write_raw,
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.debugfs_reg_access = &adrf6780_reg_access,
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};
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#define ADRF6780_CHAN_ADC(_channel) { \
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.type = IIO_ALTVOLTAGE, \
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.output = 0, \
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.indexed = 1, \
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.channel = _channel, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
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}
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#define ADRF6780_CHAN_RDAC(_channel) { \
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.type = IIO_ALTVOLTAGE, \
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.output = 1, \
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.indexed = 1, \
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.channel = _channel, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) \
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}
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#define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) { \
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.type = IIO_ALTVOLTAGE, \
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.modified = 1, \
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.output = 1, \
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.indexed = 1, \
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.channel2 = IIO_MOD_##rf_comp, \
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.channel = _channel, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) \
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}
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static const struct iio_chan_spec adrf6780_channels[] = {
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ADRF6780_CHAN_ADC(0),
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ADRF6780_CHAN_RDAC(0),
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ADRF6780_CHAN_IQ_PHASE(0, I),
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ADRF6780_CHAN_IQ_PHASE(0, Q),
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};
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static int adrf6780_reset(struct adrf6780_state *st)
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{
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int ret;
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struct spi_device *spi = st->spi;
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ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
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ADRF6780_SOFT_RESET_MSK,
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FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1));
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if (ret) {
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dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
|
||
|
|
ADRF6780_SOFT_RESET_MSK,
|
||
|
|
FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0));
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int adrf6780_init(struct adrf6780_state *st)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
unsigned int chip_id, enable_reg, enable_reg_msk;
|
||
|
|
struct spi_device *spi = st->spi;
|
||
|
|
|
||
|
|
/* Perform a software reset */
|
||
|
|
ret = adrf6780_reset(st);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id);
|
||
|
|
if (chip_id != ADRF6780_CHIP_ID) {
|
||
|
|
dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK |
|
||
|
|
ADRF6780_DETECTOR_EN_MSK |
|
||
|
|
ADRF6780_LO_BUFFER_EN_MSK |
|
||
|
|
ADRF6780_IF_MODE_EN_MSK |
|
||
|
|
ADRF6780_IQ_MODE_EN_MSK |
|
||
|
|
ADRF6780_LO_X2_EN_MSK |
|
||
|
|
ADRF6780_LO_PPF_EN_MSK |
|
||
|
|
ADRF6780_LO_EN_MSK |
|
||
|
|
ADRF6780_UC_BIAS_EN_MSK;
|
||
|
|
|
||
|
|
enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) |
|
||
|
|
FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) |
|
||
|
|
FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) |
|
||
|
|
FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) |
|
||
|
|
FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) |
|
||
|
|
FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) |
|
||
|
|
FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) |
|
||
|
|
FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) |
|
||
|
|
FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en);
|
||
|
|
|
||
|
|
ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE,
|
||
|
|
enable_reg_msk, enable_reg);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH,
|
||
|
|
ADRF6780_LO_SIDEBAND_MSK,
|
||
|
|
FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband));
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
|
||
|
|
ADRF6780_VDET_OUTPUT_SELECT_MSK,
|
||
|
|
FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void adrf6780_properties_parse(struct adrf6780_state *st)
|
||
|
|
{
|
||
|
|
struct spi_device *spi = st->spi;
|
||
|
|
|
||
|
|
st->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en");
|
||
|
|
st->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en");
|
||
|
|
st->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en");
|
||
|
|
st->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en");
|
||
|
|
st->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en");
|
||
|
|
st->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en");
|
||
|
|
st->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en");
|
||
|
|
st->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en");
|
||
|
|
st->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband");
|
||
|
|
st->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en");
|
||
|
|
}
|
||
|
|
|
||
|
|
static void adrf6780_clk_disable(void *data)
|
||
|
|
{
|
||
|
|
clk_disable_unprepare(data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void adrf6780_powerdown(void *data)
|
||
|
|
{
|
||
|
|
/* Disable all components in the Enable Register */
|
||
|
|
adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int adrf6780_probe(struct spi_device *spi)
|
||
|
|
{
|
||
|
|
struct iio_dev *indio_dev;
|
||
|
|
struct adrf6780_state *st;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
||
|
|
if (!indio_dev)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
st = iio_priv(indio_dev);
|
||
|
|
|
||
|
|
indio_dev->info = &adrf6780_info;
|
||
|
|
indio_dev->name = "adrf6780";
|
||
|
|
indio_dev->channels = adrf6780_channels;
|
||
|
|
indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels);
|
||
|
|
|
||
|
|
st->spi = spi;
|
||
|
|
|
||
|
|
adrf6780_properties_parse(st);
|
||
|
|
|
||
|
|
st->clkin = devm_clk_get(&spi->dev, "lo_in");
|
||
|
|
if (IS_ERR(st->clkin))
|
||
|
|
return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
|
||
|
|
"failed to get the LO input clock\n");
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(st->clkin);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = devm_add_action_or_reset(&spi->dev, adrf6780_clk_disable,
|
||
|
|
st->clkin);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
mutex_init(&st->lock);
|
||
|
|
|
||
|
|
ret = adrf6780_init(st);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = devm_add_action_or_reset(&spi->dev, adrf6780_powerdown, st);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
return devm_iio_device_register(&spi->dev, indio_dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct spi_device_id adrf6780_id[] = {
|
||
|
|
{ "adrf6780", 0 },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(spi, adrf6780_id);
|
||
|
|
|
||
|
|
static const struct of_device_id adrf6780_of_match[] = {
|
||
|
|
{ .compatible = "adi,adrf6780" },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, adrf6780_of_match);
|
||
|
|
|
||
|
|
static struct spi_driver adrf6780_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "adrf6780",
|
||
|
|
.of_match_table = adrf6780_of_match,
|
||
|
|
},
|
||
|
|
.probe = adrf6780_probe,
|
||
|
|
.id_table = adrf6780_id,
|
||
|
|
};
|
||
|
|
module_spi_driver(adrf6780_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
|
||
|
|
MODULE_DESCRIPTION("Analog Devices ADRF6780");
|
||
|
|
MODULE_LICENSE("GPL v2");
|