414 lines
11 KiB
C
414 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* AMD MP2 PCIe communication driver
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* Copyright 2020-2021 Advanced Micro Devices, Inc.
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*
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* Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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* Sandeep Singh <Sandeep.singh@amd.com>
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* Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmi.h>
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#include <linux/interrupt.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "amd_sfh_pcie.h"
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#define DRIVER_NAME "pcie_mp2_amd"
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#define DRIVER_DESC "AMD(R) PCIe MP2 Communication Driver"
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#define ACEL_EN BIT(0)
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#define GYRO_EN BIT(1)
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#define MAGNO_EN BIT(2)
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#define HPD_EN BIT(16)
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#define ALS_EN BIT(19)
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static int sensor_mask_override = -1;
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module_param_named(sensor_mask, sensor_mask_override, int, 0444);
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MODULE_PARM_DESC(sensor_mask, "override the detected sensors mask");
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static int amd_sfh_wait_response_v2(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts)
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{
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union cmd_response cmd_resp;
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/* Get response with status within a max of 1600 ms timeout */
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if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp,
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(cmd_resp.response_v2.response == sensor_sts &&
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cmd_resp.response_v2.status == 0 && (sid == 0xff ||
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cmd_resp.response_v2.sensor_id == sid)), 500, 1600000))
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return cmd_resp.response_v2.response;
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return SENSOR_DISABLED;
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}
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static void amd_start_sensor_v2(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
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{
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union sfh_cmd_base cmd_base;
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cmd_base.ul = 0;
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cmd_base.cmd_v2.cmd_id = ENABLE_SENSOR;
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cmd_base.cmd_v2.intr_disable = 1;
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cmd_base.cmd_v2.period = info.period;
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cmd_base.cmd_v2.sensor_id = info.sensor_idx;
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cmd_base.cmd_v2.length = 16;
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if (info.sensor_idx == als_idx)
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cmd_base.cmd_v2.mem_type = USE_C2P_REG;
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writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1);
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx)
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{
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union sfh_cmd_base cmd_base;
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cmd_base.ul = 0;
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cmd_base.cmd_v2.cmd_id = DISABLE_SENSOR;
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cmd_base.cmd_v2.intr_disable = 1;
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cmd_base.cmd_v2.period = 0;
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cmd_base.cmd_v2.sensor_id = sensor_idx;
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cmd_base.cmd_v2.length = 16;
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writeq(0x0, privdata->mmio + AMD_C2P_MSG1);
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata)
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{
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union sfh_cmd_base cmd_base;
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cmd_base.cmd_v2.cmd_id = STOP_ALL_SENSORS;
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cmd_base.cmd_v2.intr_disable = 1;
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cmd_base.cmd_v2.period = 0;
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cmd_base.cmd_v2.sensor_id = 0;
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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static void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata)
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{
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if (readl(privdata->mmio + AMD_P2C_MSG(4))) {
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writel(0, privdata->mmio + AMD_P2C_MSG(4));
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writel(0xf, privdata->mmio + AMD_P2C_MSG(5));
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}
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}
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static void amd_sfh_clear_intr(struct amd_mp2_dev *privdata)
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{
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if (privdata->mp2_ops->clear_intr)
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privdata->mp2_ops->clear_intr(privdata);
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}
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static irqreturn_t amd_sfh_irq_handler(int irq, void *data)
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{
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amd_sfh_clear_intr(data);
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return IRQ_HANDLED;
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}
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static int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata)
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{
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int rc;
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pci_intx(privdata->pdev, true);
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rc = devm_request_irq(&privdata->pdev->dev, privdata->pdev->irq,
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amd_sfh_irq_handler, 0, DRIVER_NAME, privdata);
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if (rc) {
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dev_err(&privdata->pdev->dev, "failed to request irq %d err=%d\n",
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privdata->pdev->irq, rc);
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return rc;
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}
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return 0;
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}
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static int amd_sfh_dis_sts_v2(struct amd_mp2_dev *privdata)
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{
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return (readl(privdata->mmio + AMD_P2C_MSG(1)) &
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SENSOR_DISCOVERY_STATUS_MASK) >> SENSOR_DISCOVERY_STATUS_SHIFT;
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}
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void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
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{
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union sfh_cmd_param cmd_param;
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union sfh_cmd_base cmd_base;
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/* fill up command register */
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memset(&cmd_base, 0, sizeof(cmd_base));
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cmd_base.s.cmd_id = ENABLE_SENSOR;
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cmd_base.s.period = info.period;
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cmd_base.s.sensor_id = info.sensor_idx;
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/* fill up command param register */
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memset(&cmd_param, 0, sizeof(cmd_param));
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cmd_param.s.buf_layout = 1;
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cmd_param.s.buf_length = 16;
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writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG2);
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writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx)
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{
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union sfh_cmd_base cmd_base;
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/* fill up command register */
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memset(&cmd_base, 0, sizeof(cmd_base));
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cmd_base.s.cmd_id = DISABLE_SENSOR;
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cmd_base.s.period = 0;
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cmd_base.s.sensor_id = sensor_idx;
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writeq(0x0, privdata->mmio + AMD_C2P_MSG2);
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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void amd_stop_all_sensors(struct amd_mp2_dev *privdata)
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{
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union sfh_cmd_base cmd_base;
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/* fill up command register */
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memset(&cmd_base, 0, sizeof(cmd_base));
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cmd_base.s.cmd_id = STOP_ALL_SENSORS;
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cmd_base.s.period = 0;
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cmd_base.s.sensor_id = 0;
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writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
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}
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static const struct dmi_system_id dmi_sensor_mask_overrides[] = {
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{
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 13-ag0xxx"),
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},
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.driver_data = (void *)(ACEL_EN | MAGNO_EN),
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},
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{
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 15-cp0xxx"),
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},
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.driver_data = (void *)(ACEL_EN | MAGNO_EN),
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},
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{ }
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};
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int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id)
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{
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int activestatus, num_of_sensors = 0;
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const struct dmi_system_id *dmi_id;
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if (sensor_mask_override == -1) {
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dmi_id = dmi_first_match(dmi_sensor_mask_overrides);
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if (dmi_id)
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sensor_mask_override = (long)dmi_id->driver_data;
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}
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if (sensor_mask_override >= 0) {
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activestatus = sensor_mask_override;
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} else {
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activestatus = privdata->mp2_acs >> 4;
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}
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if (ACEL_EN & activestatus)
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sensor_id[num_of_sensors++] = accel_idx;
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if (GYRO_EN & activestatus)
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sensor_id[num_of_sensors++] = gyro_idx;
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if (MAGNO_EN & activestatus)
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sensor_id[num_of_sensors++] = mag_idx;
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if (ALS_EN & activestatus)
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sensor_id[num_of_sensors++] = als_idx;
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if (HPD_EN & activestatus)
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sensor_id[num_of_sensors++] = HPD_IDX;
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return num_of_sensors;
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}
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static void amd_mp2_pci_remove(void *privdata)
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{
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struct amd_mp2_dev *mp2 = privdata;
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amd_sfh_hid_client_deinit(privdata);
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mp2->mp2_ops->stop_all(mp2);
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pci_intx(mp2->pdev, false);
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amd_sfh_clear_intr(mp2);
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}
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static const struct amd_mp2_ops amd_sfh_ops_v2 = {
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.start = amd_start_sensor_v2,
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.stop = amd_stop_sensor_v2,
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.stop_all = amd_stop_all_sensor_v2,
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.response = amd_sfh_wait_response_v2,
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.clear_intr = amd_sfh_clear_intr_v2,
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.init_intr = amd_sfh_irq_init_v2,
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.discovery_status = amd_sfh_dis_sts_v2,
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};
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static const struct amd_mp2_ops amd_sfh_ops = {
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.start = amd_start_sensor,
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.stop = amd_stop_sensor,
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.stop_all = amd_stop_all_sensors,
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};
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static void mp2_select_ops(struct amd_mp2_dev *privdata)
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{
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u8 acs;
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privdata->mp2_acs = readl(privdata->mmio + AMD_P2C_MSG3);
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acs = privdata->mp2_acs & GENMASK(3, 0);
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switch (acs) {
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case V2_STATUS:
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privdata->mp2_ops = &amd_sfh_ops_v2;
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break;
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default:
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privdata->mp2_ops = &amd_sfh_ops;
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break;
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}
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}
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static int amd_sfh_irq_init(struct amd_mp2_dev *privdata)
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{
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if (privdata->mp2_ops->init_intr)
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return privdata->mp2_ops->init_intr(privdata);
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return 0;
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}
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static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct amd_mp2_dev *privdata;
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int rc;
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privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL);
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if (!privdata)
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return -ENOMEM;
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privdata->pdev = pdev;
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dev_set_drvdata(&pdev->dev, privdata);
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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rc = pcim_iomap_regions(pdev, BIT(2), DRIVER_NAME);
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if (rc)
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return rc;
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privdata->mmio = pcim_iomap_table(pdev)[2];
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pci_set_master(pdev);
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rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
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if (rc) {
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dev_err(&pdev->dev, "failed to set DMA mask\n");
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return rc;
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}
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privdata->cl_data = devm_kzalloc(&pdev->dev, sizeof(struct amdtp_cl_data), GFP_KERNEL);
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if (!privdata->cl_data)
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return -ENOMEM;
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mp2_select_ops(privdata);
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rc = amd_sfh_irq_init(privdata);
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if (rc) {
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dev_err(&pdev->dev, "amd_sfh_irq_init failed\n");
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return rc;
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}
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rc = amd_sfh_hid_client_init(privdata);
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if (rc) {
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amd_sfh_clear_intr(privdata);
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dev_err(&pdev->dev, "amd_sfh_hid_client_init failed\n");
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return rc;
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}
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amd_sfh_clear_intr(privdata);
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return devm_add_action_or_reset(&pdev->dev, amd_mp2_pci_remove, privdata);
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}
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static int __maybe_unused amd_mp2_pci_resume(struct device *dev)
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{
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struct amd_mp2_dev *mp2 = dev_get_drvdata(dev);
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struct amdtp_cl_data *cl_data = mp2->cl_data;
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struct amd_mp2_sensor_info info;
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int i, status;
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for (i = 0; i < cl_data->num_hid_devices; i++) {
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if (cl_data->sensor_sts[i] == SENSOR_DISABLED) {
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info.period = AMD_SFH_IDLE_LOOP;
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info.sensor_idx = cl_data->sensor_idx[i];
|
||
|
|
info.dma_address = cl_data->sensor_dma_addr[i];
|
||
|
|
mp2->mp2_ops->start(mp2, info);
|
||
|
|
status = amd_sfh_wait_for_response
|
||
|
|
(mp2, cl_data->sensor_idx[i], SENSOR_ENABLED);
|
||
|
|
if (status == SENSOR_ENABLED)
|
||
|
|
cl_data->sensor_sts[i] = SENSOR_ENABLED;
|
||
|
|
dev_dbg(dev, "resume sid 0x%x status 0x%x\n",
|
||
|
|
cl_data->sensor_idx[i], cl_data->sensor_sts[i]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP));
|
||
|
|
amd_sfh_clear_intr(mp2);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __maybe_unused amd_mp2_pci_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct amd_mp2_dev *mp2 = dev_get_drvdata(dev);
|
||
|
|
struct amdtp_cl_data *cl_data = mp2->cl_data;
|
||
|
|
int i, status;
|
||
|
|
|
||
|
|
for (i = 0; i < cl_data->num_hid_devices; i++) {
|
||
|
|
if (cl_data->sensor_idx[i] != HPD_IDX &&
|
||
|
|
cl_data->sensor_sts[i] == SENSOR_ENABLED) {
|
||
|
|
mp2->mp2_ops->stop(mp2, cl_data->sensor_idx[i]);
|
||
|
|
status = amd_sfh_wait_for_response
|
||
|
|
(mp2, cl_data->sensor_idx[i], SENSOR_DISABLED);
|
||
|
|
if (status != SENSOR_ENABLED)
|
||
|
|
cl_data->sensor_sts[i] = SENSOR_DISABLED;
|
||
|
|
dev_dbg(dev, "suspend sid 0x%x status 0x%x\n",
|
||
|
|
cl_data->sensor_idx[i], cl_data->sensor_sts[i]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
cancel_delayed_work_sync(&cl_data->work_buffer);
|
||
|
|
amd_sfh_clear_intr(mp2);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static SIMPLE_DEV_PM_OPS(amd_mp2_pm_ops, amd_mp2_pci_suspend,
|
||
|
|
amd_mp2_pci_resume);
|
||
|
|
|
||
|
|
static const struct pci_device_id amd_mp2_pci_tbl[] = {
|
||
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2) },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(pci, amd_mp2_pci_tbl);
|
||
|
|
|
||
|
|
static struct pci_driver amd_mp2_pci_driver = {
|
||
|
|
.name = DRIVER_NAME,
|
||
|
|
.id_table = amd_mp2_pci_tbl,
|
||
|
|
.probe = amd_mp2_pci_probe,
|
||
|
|
.driver.pm = &amd_mp2_pm_ops,
|
||
|
|
};
|
||
|
|
module_pci_driver(amd_mp2_pci_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
||
|
|
MODULE_AUTHOR("Shyam Sundar S K <Shyam-sundar.S-k@amd.com>");
|
||
|
|
MODULE_AUTHOR("Sandeep Singh <Sandeep.singh@amd.com>");
|
||
|
|
MODULE_AUTHOR("Basavaraj Natikar <Basavaraj.Natikar@amd.com>");
|