449 lines
12 KiB
C
449 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2018 Broadcom */
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/**
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* DOC: Broadcom V3D scheduling
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*
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* The shared DRM GPU scheduler is used to coordinate submitting jobs
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* to the hardware. Each DRM fd (roughly a client process) gets its
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* own scheduler entity, which will process jobs in order. The GPU
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* scheduler will round-robin between clients to submit the next job.
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*
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* For simplicity, and in order to keep latency low for interactive
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* jobs when bulk background jobs are queued up, we submit a new job
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* to the HW only when it has completed the last one, instead of
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* filling up the CT[01]Q FIFOs with jobs. Similarly, we use
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* drm_sched_job_add_dependency() to manage the dependency between bin and
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* render, instead of having the clients submit jobs using the HW's
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* semaphores to interlock between them.
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*/
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#include <linux/kthread.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#include "v3d_trace.h"
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static struct v3d_job *
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to_v3d_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_job, base);
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}
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static struct v3d_bin_job *
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to_bin_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_bin_job, base.base);
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}
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static struct v3d_render_job *
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to_render_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_render_job, base.base);
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}
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static struct v3d_tfu_job *
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to_tfu_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_tfu_job, base.base);
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}
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static struct v3d_csd_job *
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to_csd_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_csd_job, base.base);
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}
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static void
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v3d_sched_job_free(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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v3d_job_cleanup(job);
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}
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static void
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v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job)
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{
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if (job->perfmon != v3d->active_perfmon)
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v3d_perfmon_stop(v3d, v3d->active_perfmon, true);
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if (job->perfmon && v3d->active_perfmon != job->perfmon)
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v3d_perfmon_start(v3d, job->perfmon);
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}
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static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_bin_job *job = to_bin_job(sched_job);
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struct v3d_dev *v3d = job->base.v3d;
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struct drm_device *dev = &v3d->drm;
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struct dma_fence *fence;
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unsigned long irqflags;
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if (unlikely(job->base.base.s_fence->finished.error))
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return NULL;
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/* Lock required around bin_job update vs
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* v3d_overflow_mem_work().
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*/
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spin_lock_irqsave(&v3d->job_lock, irqflags);
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v3d->bin_job = job;
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/* Clear out the overflow allocation, so we don't
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* reuse the overflow attached to a previous job.
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*/
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V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
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spin_unlock_irqrestore(&v3d->job_lock, irqflags);
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v3d_invalidate_caches(v3d);
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fence = v3d_fence_create(v3d, V3D_BIN);
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if (IS_ERR(fence))
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return NULL;
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if (job->base.irq_fence)
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dma_fence_put(job->base.irq_fence);
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job->base.irq_fence = dma_fence_get(fence);
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trace_v3d_submit_cl(dev, false, to_v3d_fence(fence)->seqno,
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job->start, job->end);
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v3d_switch_perfmon(v3d, &job->base);
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/* Set the current and end address of the control list.
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* Writing the end register is what starts the job.
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*/
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if (job->qma) {
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V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, job->qma);
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V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, job->qms);
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}
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if (job->qts) {
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V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
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V3D_CLE_CT0QTS_ENABLE |
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job->qts);
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}
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V3D_CORE_WRITE(0, V3D_CLE_CT0QBA, job->start);
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V3D_CORE_WRITE(0, V3D_CLE_CT0QEA, job->end);
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return fence;
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}
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static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_render_job *job = to_render_job(sched_job);
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struct v3d_dev *v3d = job->base.v3d;
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struct drm_device *dev = &v3d->drm;
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struct dma_fence *fence;
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if (unlikely(job->base.base.s_fence->finished.error))
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return NULL;
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v3d->render_job = job;
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/* Can we avoid this flush? We need to be careful of
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* scheduling, though -- imagine job0 rendering to texture and
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* job1 reading, and them being executed as bin0, bin1,
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* render0, render1, so that render1's flush at bin time
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* wasn't enough.
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*/
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v3d_invalidate_caches(v3d);
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fence = v3d_fence_create(v3d, V3D_RENDER);
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if (IS_ERR(fence))
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return NULL;
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if (job->base.irq_fence)
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dma_fence_put(job->base.irq_fence);
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job->base.irq_fence = dma_fence_get(fence);
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trace_v3d_submit_cl(dev, true, to_v3d_fence(fence)->seqno,
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job->start, job->end);
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v3d_switch_perfmon(v3d, &job->base);
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/* XXX: Set the QCFG */
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/* Set the current and end address of the control list.
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* Writing the end register is what starts the job.
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*/
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V3D_CORE_WRITE(0, V3D_CLE_CT1QBA, job->start);
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V3D_CORE_WRITE(0, V3D_CLE_CT1QEA, job->end);
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return fence;
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}
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static struct dma_fence *
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v3d_tfu_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_tfu_job *job = to_tfu_job(sched_job);
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struct v3d_dev *v3d = job->base.v3d;
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struct drm_device *dev = &v3d->drm;
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struct dma_fence *fence;
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fence = v3d_fence_create(v3d, V3D_TFU);
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if (IS_ERR(fence))
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return NULL;
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v3d->tfu_job = job;
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if (job->base.irq_fence)
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dma_fence_put(job->base.irq_fence);
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job->base.irq_fence = dma_fence_get(fence);
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trace_v3d_submit_tfu(dev, to_v3d_fence(fence)->seqno);
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V3D_WRITE(V3D_TFU_IIA, job->args.iia);
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V3D_WRITE(V3D_TFU_IIS, job->args.iis);
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V3D_WRITE(V3D_TFU_ICA, job->args.ica);
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V3D_WRITE(V3D_TFU_IUA, job->args.iua);
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V3D_WRITE(V3D_TFU_IOA, job->args.ioa);
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V3D_WRITE(V3D_TFU_IOS, job->args.ios);
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V3D_WRITE(V3D_TFU_COEF0, job->args.coef[0]);
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if (job->args.coef[0] & V3D_TFU_COEF0_USECOEF) {
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V3D_WRITE(V3D_TFU_COEF1, job->args.coef[1]);
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V3D_WRITE(V3D_TFU_COEF2, job->args.coef[2]);
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V3D_WRITE(V3D_TFU_COEF3, job->args.coef[3]);
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}
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/* ICFG kicks off the job. */
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V3D_WRITE(V3D_TFU_ICFG, job->args.icfg | V3D_TFU_ICFG_IOC);
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return fence;
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}
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static struct dma_fence *
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v3d_csd_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_csd_job *job = to_csd_job(sched_job);
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struct v3d_dev *v3d = job->base.v3d;
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struct drm_device *dev = &v3d->drm;
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struct dma_fence *fence;
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int i;
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v3d->csd_job = job;
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v3d_invalidate_caches(v3d);
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fence = v3d_fence_create(v3d, V3D_CSD);
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if (IS_ERR(fence))
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return NULL;
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if (job->base.irq_fence)
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dma_fence_put(job->base.irq_fence);
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job->base.irq_fence = dma_fence_get(fence);
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trace_v3d_submit_csd(dev, to_v3d_fence(fence)->seqno);
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v3d_switch_perfmon(v3d, &job->base);
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for (i = 1; i <= 6; i++)
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V3D_CORE_WRITE(0, V3D_CSD_QUEUED_CFG0 + 4 * i, job->args.cfg[i]);
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/* CFG0 write kicks off the job. */
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V3D_CORE_WRITE(0, V3D_CSD_QUEUED_CFG0, job->args.cfg[0]);
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return fence;
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}
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static struct dma_fence *
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v3d_cache_clean_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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struct v3d_dev *v3d = job->v3d;
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v3d_clean_caches(v3d);
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return NULL;
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}
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static enum drm_gpu_sched_stat
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v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
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{
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enum v3d_queue q;
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mutex_lock(&v3d->reset_lock);
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/* block scheduler */
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for (q = 0; q < V3D_MAX_QUEUES; q++)
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drm_sched_stop(&v3d->queue[q].sched, sched_job);
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if (sched_job)
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drm_sched_increase_karma(sched_job);
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/* get the GPU back into the init state */
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v3d_reset(v3d);
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for (q = 0; q < V3D_MAX_QUEUES; q++)
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drm_sched_resubmit_jobs(&v3d->queue[q].sched);
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/* Unblock schedulers and restart their jobs. */
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for (q = 0; q < V3D_MAX_QUEUES; q++) {
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drm_sched_start(&v3d->queue[q].sched, true);
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}
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mutex_unlock(&v3d->reset_lock);
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return DRM_GPU_SCHED_STAT_NOMINAL;
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}
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/* If the current address or return address have changed, then the GPU
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* has probably made progress and we should delay the reset. This
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* could fail if the GPU got in an infinite loop in the CL, but that
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* is pretty unlikely outside of an i-g-t testcase.
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*/
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static enum drm_gpu_sched_stat
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v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q,
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u32 *timedout_ctca, u32 *timedout_ctra)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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struct v3d_dev *v3d = job->v3d;
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u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q));
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u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q));
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if (*timedout_ctca != ctca || *timedout_ctra != ctra) {
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*timedout_ctca = ctca;
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*timedout_ctra = ctra;
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return DRM_GPU_SCHED_STAT_NOMINAL;
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}
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return v3d_gpu_reset_for_timeout(v3d, sched_job);
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}
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static enum drm_gpu_sched_stat
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v3d_bin_job_timedout(struct drm_sched_job *sched_job)
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{
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struct v3d_bin_job *job = to_bin_job(sched_job);
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return v3d_cl_job_timedout(sched_job, V3D_BIN,
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&job->timedout_ctca, &job->timedout_ctra);
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}
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static enum drm_gpu_sched_stat
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v3d_render_job_timedout(struct drm_sched_job *sched_job)
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{
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struct v3d_render_job *job = to_render_job(sched_job);
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return v3d_cl_job_timedout(sched_job, V3D_RENDER,
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&job->timedout_ctca, &job->timedout_ctra);
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}
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static enum drm_gpu_sched_stat
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v3d_generic_job_timedout(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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return v3d_gpu_reset_for_timeout(job->v3d, sched_job);
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}
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static enum drm_gpu_sched_stat
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v3d_csd_job_timedout(struct drm_sched_job *sched_job)
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{
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struct v3d_csd_job *job = to_csd_job(sched_job);
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struct v3d_dev *v3d = job->base.v3d;
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u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4);
|
||
|
|
|
||
|
|
/* If we've made progress, skip reset and let the timer get
|
||
|
|
* rearmed.
|
||
|
|
*/
|
||
|
|
if (job->timedout_batches != batches) {
|
||
|
|
job->timedout_batches = batches;
|
||
|
|
return DRM_GPU_SCHED_STAT_NOMINAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return v3d_gpu_reset_for_timeout(v3d, sched_job);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct drm_sched_backend_ops v3d_bin_sched_ops = {
|
||
|
|
.run_job = v3d_bin_job_run,
|
||
|
|
.timedout_job = v3d_bin_job_timedout,
|
||
|
|
.free_job = v3d_sched_job_free,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_sched_backend_ops v3d_render_sched_ops = {
|
||
|
|
.run_job = v3d_render_job_run,
|
||
|
|
.timedout_job = v3d_render_job_timedout,
|
||
|
|
.free_job = v3d_sched_job_free,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_sched_backend_ops v3d_tfu_sched_ops = {
|
||
|
|
.run_job = v3d_tfu_job_run,
|
||
|
|
.timedout_job = v3d_generic_job_timedout,
|
||
|
|
.free_job = v3d_sched_job_free,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_sched_backend_ops v3d_csd_sched_ops = {
|
||
|
|
.run_job = v3d_csd_job_run,
|
||
|
|
.timedout_job = v3d_csd_job_timedout,
|
||
|
|
.free_job = v3d_sched_job_free
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_sched_backend_ops v3d_cache_clean_sched_ops = {
|
||
|
|
.run_job = v3d_cache_clean_job_run,
|
||
|
|
.timedout_job = v3d_generic_job_timedout,
|
||
|
|
.free_job = v3d_sched_job_free
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
v3d_sched_init(struct v3d_dev *v3d)
|
||
|
|
{
|
||
|
|
int hw_jobs_limit = 1;
|
||
|
|
int job_hang_limit = 0;
|
||
|
|
int hang_limit_ms = 500;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
|
||
|
|
&v3d_bin_sched_ops,
|
||
|
|
hw_jobs_limit, job_hang_limit,
|
||
|
|
msecs_to_jiffies(hang_limit_ms), NULL,
|
||
|
|
NULL, "v3d_bin", v3d->drm.dev);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
|
||
|
|
&v3d_render_sched_ops,
|
||
|
|
hw_jobs_limit, job_hang_limit,
|
||
|
|
msecs_to_jiffies(hang_limit_ms), NULL,
|
||
|
|
NULL, "v3d_render", v3d->drm.dev);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
|
||
|
|
&v3d_tfu_sched_ops,
|
||
|
|
hw_jobs_limit, job_hang_limit,
|
||
|
|
msecs_to_jiffies(hang_limit_ms), NULL,
|
||
|
|
NULL, "v3d_tfu", v3d->drm.dev);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
if (v3d_has_csd(v3d)) {
|
||
|
|
ret = drm_sched_init(&v3d->queue[V3D_CSD].sched,
|
||
|
|
&v3d_csd_sched_ops,
|
||
|
|
hw_jobs_limit, job_hang_limit,
|
||
|
|
msecs_to_jiffies(hang_limit_ms), NULL,
|
||
|
|
NULL, "v3d_csd", v3d->drm.dev);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched,
|
||
|
|
&v3d_cache_clean_sched_ops,
|
||
|
|
hw_jobs_limit, job_hang_limit,
|
||
|
|
msecs_to_jiffies(hang_limit_ms), NULL,
|
||
|
|
NULL, "v3d_cache_clean", v3d->drm.dev);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
v3d_sched_fini(v3d);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
v3d_sched_fini(struct v3d_dev *v3d)
|
||
|
|
{
|
||
|
|
enum v3d_queue q;
|
||
|
|
|
||
|
|
for (q = 0; q < V3D_MAX_QUEUES; q++) {
|
||
|
|
if (v3d->queue[q].sched.ready)
|
||
|
|
drm_sched_fini(&v3d->queue[q].sched);
|
||
|
|
}
|
||
|
|
}
|