467 lines
10 KiB
C
467 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2021, NVIDIA Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <soc/tegra/pmc.h>
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#include "drm.h"
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#include "falcon.h"
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#include "vic.h"
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struct nvdec_config {
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const char *firmware;
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unsigned int version;
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bool supports_sid;
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};
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struct nvdec {
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struct falcon falcon;
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void __iomem *regs;
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struct tegra_drm_client client;
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struct host1x_channel *channel;
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struct device *dev;
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struct clk *clk;
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/* Platform configuration */
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const struct nvdec_config *config;
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};
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static inline struct nvdec *to_nvdec(struct tegra_drm_client *client)
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{
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return container_of(client, struct nvdec, client);
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}
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static inline void nvdec_writel(struct nvdec *nvdec, u32 value,
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unsigned int offset)
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{
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writel(value, nvdec->regs + offset);
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}
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static int nvdec_boot(struct nvdec *nvdec)
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{
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#ifdef CONFIG_IOMMU_API
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struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev);
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#endif
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int err;
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#ifdef CONFIG_IOMMU_API
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if (nvdec->config->supports_sid && spec) {
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u32 value;
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value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
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nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
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if (spec->num_ids > 0) {
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value = spec->ids[0] & 0xffff;
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nvdec_writel(nvdec, value, VIC_THI_STREAMID0);
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nvdec_writel(nvdec, value, VIC_THI_STREAMID1);
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}
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}
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#endif
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err = falcon_boot(&nvdec->falcon);
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if (err < 0)
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return err;
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err = falcon_wait_idle(&nvdec->falcon);
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if (err < 0) {
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dev_err(nvdec->dev, "falcon boot timed out\n");
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return err;
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}
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return 0;
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}
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static int nvdec_init(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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struct tegra_drm *tegra = dev->dev_private;
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struct nvdec *nvdec = to_nvdec(drm);
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int err;
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err = host1x_client_iommu_attach(client);
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if (err < 0 && err != -ENODEV) {
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dev_err(nvdec->dev, "failed to attach to domain: %d\n", err);
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return err;
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}
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nvdec->channel = host1x_channel_request(client);
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if (!nvdec->channel) {
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err = -ENOMEM;
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goto detach;
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}
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client->syncpts[0] = host1x_syncpt_request(client, 0);
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if (!client->syncpts[0]) {
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err = -ENOMEM;
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goto free_channel;
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}
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pm_runtime_enable(client->dev);
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pm_runtime_use_autosuspend(client->dev);
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pm_runtime_set_autosuspend_delay(client->dev, 500);
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err = tegra_drm_register_client(tegra, drm);
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if (err < 0)
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goto disable_rpm;
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/*
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* Inherit the DMA parameters (such as maximum segment size) from the
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* parent host1x device.
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*/
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client->dev->dma_parms = client->host->dma_parms;
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return 0;
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disable_rpm:
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pm_runtime_dont_use_autosuspend(client->dev);
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pm_runtime_force_suspend(client->dev);
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host1x_syncpt_put(client->syncpts[0]);
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free_channel:
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host1x_channel_put(nvdec->channel);
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detach:
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host1x_client_iommu_detach(client);
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return err;
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}
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static int nvdec_exit(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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struct tegra_drm *tegra = dev->dev_private;
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struct nvdec *nvdec = to_nvdec(drm);
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int err;
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/* avoid a dangling pointer just in case this disappears */
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client->dev->dma_parms = NULL;
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err = tegra_drm_unregister_client(tegra, drm);
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if (err < 0)
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return err;
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pm_runtime_dont_use_autosuspend(client->dev);
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pm_runtime_force_suspend(client->dev);
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host1x_syncpt_put(client->syncpts[0]);
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host1x_channel_put(nvdec->channel);
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host1x_client_iommu_detach(client);
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nvdec->channel = NULL;
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if (client->group) {
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dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys,
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nvdec->falcon.firmware.size, DMA_TO_DEVICE);
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tegra_drm_free(tegra, nvdec->falcon.firmware.size,
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nvdec->falcon.firmware.virt,
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nvdec->falcon.firmware.iova);
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} else {
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dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size,
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nvdec->falcon.firmware.virt,
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nvdec->falcon.firmware.iova);
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}
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return 0;
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}
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static const struct host1x_client_ops nvdec_client_ops = {
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.init = nvdec_init,
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.exit = nvdec_exit,
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};
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static int nvdec_load_firmware(struct nvdec *nvdec)
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{
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struct host1x_client *client = &nvdec->client.base;
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struct tegra_drm *tegra = nvdec->client.drm;
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dma_addr_t iova;
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size_t size;
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void *virt;
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int err;
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if (nvdec->falcon.firmware.virt)
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return 0;
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err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);
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if (err < 0)
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return err;
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size = nvdec->falcon.firmware.size;
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if (!client->group) {
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virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL);
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err = dma_mapping_error(nvdec->dev, iova);
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if (err < 0)
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return err;
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} else {
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virt = tegra_drm_alloc(tegra, size, &iova);
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}
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nvdec->falcon.firmware.virt = virt;
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nvdec->falcon.firmware.iova = iova;
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err = falcon_load_firmware(&nvdec->falcon);
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if (err < 0)
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goto cleanup;
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/*
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* In this case we have received an IOVA from the shared domain, so we
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* need to make sure to get the physical address so that the DMA API
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* knows what memory pages to flush the cache for.
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*/
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if (client->group) {
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dma_addr_t phys;
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phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE);
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err = dma_mapping_error(nvdec->dev, phys);
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if (err < 0)
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goto cleanup;
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nvdec->falcon.firmware.phys = phys;
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}
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return 0;
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cleanup:
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if (!client->group)
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dma_free_coherent(nvdec->dev, size, virt, iova);
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else
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tegra_drm_free(tegra, size, virt, iova);
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return err;
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}
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static __maybe_unused int nvdec_runtime_resume(struct device *dev)
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{
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struct nvdec *nvdec = dev_get_drvdata(dev);
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int err;
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err = clk_prepare_enable(nvdec->clk);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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err = nvdec_load_firmware(nvdec);
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if (err < 0)
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goto disable;
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err = nvdec_boot(nvdec);
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if (err < 0)
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goto disable;
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return 0;
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disable:
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clk_disable_unprepare(nvdec->clk);
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return err;
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}
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static __maybe_unused int nvdec_runtime_suspend(struct device *dev)
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{
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struct nvdec *nvdec = dev_get_drvdata(dev);
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host1x_channel_stop(nvdec->channel);
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clk_disable_unprepare(nvdec->clk);
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return 0;
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}
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static int nvdec_open_channel(struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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struct nvdec *nvdec = to_nvdec(client);
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context->channel = host1x_channel_get(nvdec->channel);
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if (!context->channel)
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return -ENOMEM;
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return 0;
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}
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static void nvdec_close_channel(struct tegra_drm_context *context)
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{
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host1x_channel_put(context->channel);
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}
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static const struct tegra_drm_client_ops nvdec_ops = {
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.open_channel = nvdec_open_channel,
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.close_channel = nvdec_close_channel,
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.submit = tegra_drm_submit,
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};
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#define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
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static const struct nvdec_config nvdec_t210_config = {
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.firmware = NVIDIA_TEGRA_210_NVDEC_FIRMWARE,
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.version = 0x21,
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.supports_sid = false,
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};
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#define NVIDIA_TEGRA_186_NVDEC_FIRMWARE "nvidia/tegra186/nvdec.bin"
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static const struct nvdec_config nvdec_t186_config = {
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.firmware = NVIDIA_TEGRA_186_NVDEC_FIRMWARE,
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.version = 0x18,
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.supports_sid = true,
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};
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#define NVIDIA_TEGRA_194_NVDEC_FIRMWARE "nvidia/tegra194/nvdec.bin"
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static const struct nvdec_config nvdec_t194_config = {
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.firmware = NVIDIA_TEGRA_194_NVDEC_FIRMWARE,
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.version = 0x19,
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.supports_sid = true,
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};
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static const struct of_device_id tegra_nvdec_of_match[] = {
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{ .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config },
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{ .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config },
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{ .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_nvdec_of_match);
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static int nvdec_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct host1x_syncpt **syncpts;
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struct nvdec *nvdec;
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u32 host_class;
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int err;
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/* inherit DMA mask from host1x parent */
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err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
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return err;
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}
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nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL);
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if (!nvdec)
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return -ENOMEM;
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nvdec->config = of_device_get_match_data(dev);
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syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
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if (!syncpts)
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return -ENOMEM;
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nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(nvdec->regs))
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return PTR_ERR(nvdec->regs);
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nvdec->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(nvdec->clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(nvdec->clk);
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}
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err = clk_set_rate(nvdec->clk, ULONG_MAX);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set clock rate\n");
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return err;
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}
|
||
|
|
|
||
|
|
err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class);
|
||
|
|
if (err < 0)
|
||
|
|
host_class = HOST1X_CLASS_NVDEC;
|
||
|
|
|
||
|
|
nvdec->falcon.dev = dev;
|
||
|
|
nvdec->falcon.regs = nvdec->regs;
|
||
|
|
|
||
|
|
err = falcon_init(&nvdec->falcon);
|
||
|
|
if (err < 0)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, nvdec);
|
||
|
|
|
||
|
|
INIT_LIST_HEAD(&nvdec->client.base.list);
|
||
|
|
nvdec->client.base.ops = &nvdec_client_ops;
|
||
|
|
nvdec->client.base.dev = dev;
|
||
|
|
nvdec->client.base.class = host_class;
|
||
|
|
nvdec->client.base.syncpts = syncpts;
|
||
|
|
nvdec->client.base.num_syncpts = 1;
|
||
|
|
nvdec->dev = dev;
|
||
|
|
|
||
|
|
INIT_LIST_HEAD(&nvdec->client.list);
|
||
|
|
nvdec->client.version = nvdec->config->version;
|
||
|
|
nvdec->client.ops = &nvdec_ops;
|
||
|
|
|
||
|
|
err = host1x_client_register(&nvdec->client.base);
|
||
|
|
if (err < 0) {
|
||
|
|
dev_err(dev, "failed to register host1x client: %d\n", err);
|
||
|
|
goto exit_falcon;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
exit_falcon:
|
||
|
|
falcon_exit(&nvdec->falcon);
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int nvdec_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct nvdec *nvdec = platform_get_drvdata(pdev);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
err = host1x_client_unregister(&nvdec->client.base);
|
||
|
|
if (err < 0) {
|
||
|
|
dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
|
||
|
|
err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
falcon_exit(&nvdec->falcon);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dev_pm_ops nvdec_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(nvdec_runtime_suspend, nvdec_runtime_resume, NULL)
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||
|
|
pm_runtime_force_resume)
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_driver tegra_nvdec_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "tegra-nvdec",
|
||
|
|
.of_match_table = tegra_nvdec_of_match,
|
||
|
|
.pm = &nvdec_pm_ops
|
||
|
|
},
|
||
|
|
.probe = nvdec_probe,
|
||
|
|
.remove = nvdec_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
|
||
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_210_NVDEC_FIRMWARE);
|
||
|
|
#endif
|
||
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
|
||
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_186_NVDEC_FIRMWARE);
|
||
|
|
#endif
|
||
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
|
||
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_194_NVDEC_FIRMWARE);
|
||
|
|
#endif
|