347 lines
12 KiB
C
347 lines
12 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Monk.liu@amd.com
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*/
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#ifndef AMDGPU_VIRT_H
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#define AMDGPU_VIRT_H
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#include "amdgv_sriovmsg.h"
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#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
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#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
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#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
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#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
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#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
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/* flags for indirect register access path supported by rlcg for sriov */
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#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
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#define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
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#define AMDGPU_RLCG_GC_READ (0x1 << 28)
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#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
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/* error code for indirect register access path supported by rlcg for sriov */
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#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
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#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
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#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
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#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
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/* all asic after AI use this offset */
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#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
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/* tonga/fiji use this offset */
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#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
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enum amdgpu_sriov_vf_mode {
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SRIOV_VF_MODE_BARE_METAL = 0,
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SRIOV_VF_MODE_ONE_VF,
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SRIOV_VF_MODE_MULTI_VF,
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};
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struct amdgpu_mm_table {
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struct amdgpu_bo *bo;
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uint32_t *cpu_addr;
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uint64_t gpu_addr;
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};
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#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
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/* struct error_entry - amdgpu VF error information. */
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struct amdgpu_vf_error_buffer {
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struct mutex lock;
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int read_count;
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int write_count;
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uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
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uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
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uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
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};
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/**
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* struct amdgpu_virt_ops - amdgpu device virt operations
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*/
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struct amdgpu_virt_ops {
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int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*req_init_data)(struct amdgpu_device *adev);
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int (*reset_gpu)(struct amdgpu_device *adev);
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int (*wait_reset)(struct amdgpu_device *adev);
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void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
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};
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/*
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* Firmware Reserve Frame buffer
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*/
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struct amdgpu_virt_fw_reserve {
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struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
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struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
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unsigned int checksum_key;
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};
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/*
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* Legacy GIM header
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*
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* Defination between PF and VF
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* Structures forcibly aligned to 4 to keep the same style as PF.
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*/
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#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
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#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
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(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
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enum AMDGIM_FEATURE_FLAG {
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/* GIM supports feature of Error log collecting */
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AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
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/* GIM supports feature of loading uCodes */
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AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
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/* VRAM LOST by GIM */
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AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
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/* MM bandwidth */
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AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
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/* PP ONE VF MODE in GIM */
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AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
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/* Indirect Reg Access enabled */
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AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
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};
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enum AMDGIM_REG_ACCESS_FLAG {
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/* Use PSP to program IH_RB_CNTL */
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AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
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/* Use RLC to program MMHUB regs */
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AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
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/* Use RLC to program GC regs */
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AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
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};
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struct amdgim_pf2vf_info_v1 {
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/* header contains size and version */
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struct amd_sriov_msg_pf2vf_info_header header;
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/* max_width * max_height */
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unsigned int uvd_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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unsigned int uvd_enc_max_bandwidth;
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/* max_width * max_height */
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unsigned int vce_enc_max_pixels_count;
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/* 16x16 pixels/sec, codec independent */
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unsigned int vce_enc_max_bandwidth;
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/* MEC FW position in kb from the start of visible frame buffer */
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unsigned int mecfw_kboffset;
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/* The features flags of the GIM driver supports. */
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unsigned int feature_flags;
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/* use private key from mailbox 2 to create chueksum */
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unsigned int checksum;
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} __aligned(4);
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struct amdgim_vf2pf_info_v1 {
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/* header contains size and version */
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struct amd_sriov_msg_vf2pf_info_header header;
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/* driver version */
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char driver_version[64];
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/* driver certification, 1=WHQL, 0=None */
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unsigned int driver_cert;
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/* guest OS type and version: need a define */
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unsigned int os_info;
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/* in the unit of 1M */
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unsigned int fb_usage;
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/* guest gfx engine usage percentage */
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unsigned int gfx_usage;
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/* guest gfx engine health percentage */
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unsigned int gfx_health;
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/* guest compute engine usage percentage */
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unsigned int compute_usage;
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/* guest compute engine health percentage */
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unsigned int compute_health;
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/* guest vce engine usage percentage. 0xffff means N/A. */
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unsigned int vce_enc_usage;
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/* guest vce engine health percentage. 0xffff means N/A. */
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unsigned int vce_enc_health;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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unsigned int uvd_enc_usage;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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unsigned int uvd_enc_health;
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unsigned int checksum;
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} __aligned(4);
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struct amdgim_vf2pf_info_v2 {
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/* header contains size and version */
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struct amd_sriov_msg_vf2pf_info_header header;
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uint32_t checksum;
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/* driver version */
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uint8_t driver_version[64];
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/* driver certification, 1=WHQL, 0=None */
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uint32_t driver_cert;
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/* guest OS type and version: need a define */
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uint32_t os_info;
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/* in the unit of 1M */
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uint32_t fb_usage;
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/* guest gfx engine usage percentage */
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uint32_t gfx_usage;
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/* guest gfx engine health percentage */
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uint32_t gfx_health;
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/* guest compute engine usage percentage */
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uint32_t compute_usage;
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/* guest compute engine health percentage */
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uint32_t compute_health;
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/* guest vce engine usage percentage. 0xffff means N/A. */
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uint32_t vce_enc_usage;
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/* guest vce engine health percentage. 0xffff means N/A. */
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uint32_t vce_enc_health;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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uint32_t uvd_enc_usage;
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/* guest uvd engine usage percentage. 0xffff means N/A. */
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uint32_t uvd_enc_health;
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uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
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} __aligned(4);
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struct amdgpu_virt_ras_err_handler_data {
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/* point to bad page records array */
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struct eeprom_table_record *bps;
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/* point to reserved bo array */
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struct amdgpu_bo **bps_bo;
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/* the count of entries */
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int count;
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/* last reserved entry's index + 1 */
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int last_reserved;
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};
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/* GPU virtualization */
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struct amdgpu_virt {
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uint32_t caps;
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struct amdgpu_bo *csa_obj;
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void *csa_cpu_addr;
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bool chained_ib_support;
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uint32_t reg_val_offs;
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struct amdgpu_irq_src ack_irq;
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struct amdgpu_irq_src rcv_irq;
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struct work_struct flr_work;
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struct amdgpu_mm_table mm_table;
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const struct amdgpu_virt_ops *ops;
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struct amdgpu_vf_error_buffer vf_errors;
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struct amdgpu_virt_fw_reserve fw_reserve;
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uint32_t gim_feature;
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uint32_t reg_access_mode;
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int req_init_data_ver;
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bool tdr_debug;
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struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
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bool ras_init_done;
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uint32_t reg_access;
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/* vf2pf message */
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struct delayed_work vf2pf_work;
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uint32_t vf2pf_update_interval_ms;
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/* multimedia bandwidth config */
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bool is_mm_bw_enabled;
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uint32_t decode_max_dimension_pixels;
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uint32_t decode_max_frame_pixels;
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uint32_t encode_max_dimension_pixels;
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uint32_t encode_max_frame_pixels;
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};
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struct amdgpu_video_codec_info;
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#define amdgpu_sriov_enabled(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
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#define amdgpu_sriov_vf(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
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#define amdgpu_sriov_bios(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
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#define amdgpu_sriov_runtime(adev) \
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((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
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#define amdgpu_sriov_fullaccess(adev) \
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(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
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#define amdgpu_sriov_reg_indirect_en(adev) \
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(amdgpu_sriov_vf((adev)) && \
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((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
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#define amdgpu_sriov_reg_indirect_ih(adev) \
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(amdgpu_sriov_vf((adev)) && \
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((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
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#define amdgpu_sriov_reg_indirect_mmhub(adev) \
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(amdgpu_sriov_vf((adev)) && \
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((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
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#define amdgpu_sriov_reg_indirect_gc(adev) \
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(amdgpu_sriov_vf((adev)) && \
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((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
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#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
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(amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
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#define amdgpu_passthrough(adev) \
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((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
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static inline bool is_virtual_machine(void)
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{
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#if defined(CONFIG_X86)
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return boot_cpu_has(X86_FEATURE_HYPERVISOR);
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#elif defined(CONFIG_ARM64)
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return !is_kernel_in_hyp_mode();
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#else
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return false;
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#endif
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}
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#define amdgpu_sriov_is_pp_one_vf(adev) \
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((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
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#define amdgpu_sriov_is_debug(adev) \
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((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
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#define amdgpu_sriov_is_normal(adev) \
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((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t rreg1,
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uint32_t ref, uint32_t mask);
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
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void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
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int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
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int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
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void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
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void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
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void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
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void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
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||
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void amdgpu_detect_virtualization(struct amdgpu_device *adev);
|
||
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||
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bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
|
||
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int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
|
||
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void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
|
||
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|
||
|
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enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
|
||
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|
||
|
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void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
|
||
|
|
struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
|
||
|
|
void amdgpu_sriov_wreg(struct amdgpu_device *adev,
|
||
|
|
u32 offset, u32 value,
|
||
|
|
u32 acc_flags, u32 hwip);
|
||
|
|
u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
|
||
|
|
u32 offset, u32 acc_flags, u32 hwip);
|
||
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|
#endif
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