275 lines
8.2 KiB
C
275 lines
8.2 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_rlc.h"
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/**
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* amdgpu_gfx_rlc_enter_safe_mode - Set RLC into safe mode
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*
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* @adev: amdgpu_device pointer
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*
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* Set RLC enter into safe mode if RLC is enabled and haven't in safe mode.
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*/
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void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
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{
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if (adev->gfx.rlc.in_safe_mode)
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return;
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/* if RLC is not enabled, do nothing */
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if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
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return;
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if (adev->cg_flags &
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(AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_3D_CGCG)) {
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adev->gfx.rlc.funcs->set_safe_mode(adev);
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adev->gfx.rlc.in_safe_mode = true;
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}
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}
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/**
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* amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode
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*
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* @adev: amdgpu_device pointer
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*
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* Set RLC exit safe mode if RLC is enabled and have entered into safe mode.
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*/
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void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)
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{
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if (!(adev->gfx.rlc.in_safe_mode))
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return;
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/* if RLC is not enabled, do nothing */
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if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
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return;
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if (adev->cg_flags &
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(AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_3D_CGCG)) {
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adev->gfx.rlc.funcs->unset_safe_mode(adev);
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adev->gfx.rlc.in_safe_mode = false;
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}
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}
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/**
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* amdgpu_gfx_rlc_init_sr - Init save restore block
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*
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* @adev: amdgpu_device pointer
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* @dws: the size of save restore block
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*
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* Allocate and setup value to save restore block of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)
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{
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const u32 *src_ptr;
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volatile u32 *dst_ptr;
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u32 i;
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int r;
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/* allocate save restore block */
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r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.save_restore_obj,
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&adev->gfx.rlc.save_restore_gpu_addr,
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(void **)&adev->gfx.rlc.sr_ptr);
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if (r) {
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dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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/* write the sr buffer */
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src_ptr = adev->gfx.rlc.reg_list;
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dst_ptr = adev->gfx.rlc.sr_ptr;
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for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
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dst_ptr[i] = cpu_to_le32(src_ptr[i]);
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amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_init_csb - Init clear state block
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate and setup value to clear state block of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
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{
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u32 dws;
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int r;
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/* allocate clear state block */
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adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
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r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_init_cpt - Init cp table
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate and setup value to cp table of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create cp table bo\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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/* set up the cp table */
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amdgpu_gfx_rlc_setup_cp_table(adev);
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amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_setup_cp_table - setup cp the buffer of cp table
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*
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* @adev: amdgpu_device pointer
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*
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* Write cp firmware data into cp table.
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*/
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void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev)
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{
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const __le32 *fw_data;
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volatile u32 *dst_ptr;
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int me, i, max_me;
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u32 bo_offset = 0;
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u32 table_offset, table_size;
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max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev);
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/* write the cp table buffer */
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dst_ptr = adev->gfx.rlc.cp_table_ptr;
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for (me = 0; me < max_me; me++) {
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if (me == 0) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.ce_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 1) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.pfp_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 2) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.me_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 3) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 4) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec2_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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}
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for (i = 0; i < table_size; i ++) {
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dst_ptr[bo_offset + i] =
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cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
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}
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bo_offset += table_size;
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}
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}
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/**
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* amdgpu_gfx_rlc_fini - Free BO which used for RLC
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*
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* @adev: amdgpu_device pointer
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*
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* Free three BO which is used for rlc_save_restore_block, rlc_clear_state_block
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* and rlc_jump_table_block.
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*/
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void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev)
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{
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/* save restore block */
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if (adev->gfx.rlc.save_restore_obj) {
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amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj,
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&adev->gfx.rlc.save_restore_gpu_addr,
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(void **)&adev->gfx.rlc.sr_ptr);
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}
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/* clear state block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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/* jump table block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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}
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