461 lines
12 KiB
C
461 lines
12 KiB
C
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/debugfs.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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/*
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* Rings
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* Most engines on the GPU are fed via ring buffers. Ring
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* buffers are areas of GPU accessible memory that the host
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* writes commands into and the GPU reads commands out of.
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* There is a rptr (read pointer) that determines where the
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* GPU is currently reading, and a wptr (write pointer)
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* which determines where the host has written. When the
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* pointers are equal, the ring is idle. When the host
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* writes commands to the ring buffer, it increments the
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* wptr. The GPU then starts fetching commands and executes
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* them until the pointers are equal again.
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*/
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/**
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* amdgpu_ring_alloc - allocate space on the ring buffer
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*
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* @ring: amdgpu_ring structure holding ring information
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* @ndw: number of dwords to allocate in the ring buffer
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*
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* Allocate @ndw dwords in the ring buffer (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
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{
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
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/* Make sure we aren't trying to allocate more space
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* than the maximum for one submission
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*/
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if (WARN_ON_ONCE(ndw > ring->max_dw))
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return -ENOMEM;
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ring->count_dw = ndw;
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ring->wptr_old = ring->wptr;
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if (ring->funcs->begin_use)
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ring->funcs->begin_use(ring);
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return 0;
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}
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/** amdgpu_ring_insert_nop - insert NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @count: the number of NOP packets to insert
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*
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* This is the generic insert_nop function for rings except SDMA
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*/
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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amdgpu_ring_write(ring, ring->funcs->nop);
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}
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/**
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* amdgpu_ring_generic_pad_ib - pad IB with NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @ib: IB to add NOP packets to
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*
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* This is the generic pad_ib function for rings except SDMA
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*/
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
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{
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while (ib->length_dw & ring->funcs->align_mask)
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ib->ptr[ib->length_dw++] = ring->funcs->nop;
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}
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/**
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* amdgpu_ring_commit - tell the GPU to execute the new
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* commands on the ring buffer
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*
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* @ring: amdgpu_ring structure holding ring information
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*
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* Update the wptr (write pointer) to tell the GPU to
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* execute new commands on the ring buffer (all asics).
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*/
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void amdgpu_ring_commit(struct amdgpu_ring *ring)
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{
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uint32_t count;
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/* We pad to match fetch size */
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count = ring->funcs->align_mask + 1 -
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(ring->wptr & ring->funcs->align_mask);
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count %= ring->funcs->align_mask + 1;
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ring->funcs->insert_nop(ring, count);
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mb();
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amdgpu_ring_set_wptr(ring);
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if (ring->funcs->end_use)
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ring->funcs->end_use(ring);
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}
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/**
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* amdgpu_ring_undo - reset the wptr
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*
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* @ring: amdgpu_ring structure holding ring information
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*
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* Reset the driver's copy of the wptr (all asics).
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*/
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void amdgpu_ring_undo(struct amdgpu_ring *ring)
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{
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ring->wptr = ring->wptr_old;
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if (ring->funcs->end_use)
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ring->funcs->end_use(ring);
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}
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/**
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* amdgpu_ring_init - init driver ring struct.
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @max_dw: maximum number of dw for ring alloc
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* @irq_src: interrupt source to use for this ring
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* @irq_type: interrupt type to use for this ring
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* @hw_prio: ring priority (NORMAL/HIGH)
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* @sched_score: optional score atomic shared with other schedulers
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*
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* Initialize the driver information for the selected ring (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned int max_dw, struct amdgpu_irq_src *irq_src,
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unsigned int irq_type, unsigned int hw_prio,
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atomic_t *sched_score)
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{
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int r;
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int sched_hw_submission = amdgpu_sched_hw_submission;
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u32 *num_sched;
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u32 hw_ip;
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/* Set the hw submission limit higher for KIQ because
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* it's used for a number of gfx/compute tasks by both
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* KFD and KGD which may have outstanding fences and
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* it doesn't really use the gpu scheduler anyway;
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* KIQ tasks get submitted directly to the ring.
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*/
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if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
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sched_hw_submission = max(sched_hw_submission, 256);
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else if (ring == &adev->sdma.instance[0].page)
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sched_hw_submission = 256;
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if (ring->adev == NULL) {
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if (adev->num_rings >= AMDGPU_MAX_RINGS)
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return -EINVAL;
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ring->adev = adev;
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ring->idx = adev->num_rings++;
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adev->rings[ring->idx] = ring;
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ring->num_hw_submission = sched_hw_submission;
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ring->sched_score = sched_score;
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ring->vmid_wait = dma_fence_get_stub();
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r = amdgpu_fence_driver_init_ring(ring);
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if (r)
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->fence_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
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if (r) {
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dev_err(adev->dev,
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"(%d) ring trail_fence_offs wb alloc failed\n", r);
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return r;
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}
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ring->trail_fence_gpu_addr =
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adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
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ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
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r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
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return r;
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}
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ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
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ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
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/* always set cond_exec_polling to CONTINUE */
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*ring->cond_exe_cpu_addr = 1;
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r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
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if (r) {
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dev_err(adev->dev, "failed initializing fences (%d).\n", r);
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return r;
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}
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ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
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ring->buf_mask = (ring->ring_size / 4) - 1;
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ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
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0xffffffffffffffff : ring->buf_mask;
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/* Allocate ring buffer */
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if (ring->ring_obj == NULL) {
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r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT,
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&ring->ring_obj,
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&ring->gpu_addr,
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(void **)&ring->ring);
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if (r) {
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dev_err(adev->dev, "(%d) ring create failed\n", r);
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return r;
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}
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amdgpu_ring_clear_ring(ring);
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}
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ring->max_dw = max_dw;
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ring->hw_prio = hw_prio;
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if (!ring->no_scheduler) {
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hw_ip = ring->funcs->type;
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num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
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adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
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&ring->sched;
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}
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return 0;
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}
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/**
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* amdgpu_ring_fini - tear down the driver ring struct.
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*
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* @ring: amdgpu_ring structure holding ring information
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*
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* Tear down the driver information for the selected ring (all asics).
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*/
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void amdgpu_ring_fini(struct amdgpu_ring *ring)
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{
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/* Not to finish a ring which is not initialized */
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if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
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return;
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ring->sched.ready = false;
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amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
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amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
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amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
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amdgpu_device_wb_free(ring->adev, ring->fence_offs);
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amdgpu_bo_free_kernel(&ring->ring_obj,
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&ring->gpu_addr,
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(void **)&ring->ring);
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dma_fence_put(ring->vmid_wait);
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ring->vmid_wait = NULL;
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ring->me = 0;
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ring->adev->rings[ring->idx] = NULL;
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}
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/**
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* amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
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*
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* @ring: ring to write to
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* @reg0: register to write
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* @reg1: register to wait on
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* @ref: reference value to write/wait on
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* @mask: mask to wait on
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*
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* Helper for rings that don't support write and wait in a
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* single oneshot packet.
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*/
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void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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{
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amdgpu_ring_emit_wreg(ring, reg0, ref);
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amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
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}
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/**
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* amdgpu_ring_soft_recovery - try to soft recover a ring lockup
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*
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* @ring: ring to try the recovery on
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* @vmid: VMID we try to get going again
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* @fence: timedout fence
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*
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* Tries to get a ring proceeding again when it is stuck.
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*/
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bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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struct dma_fence *fence)
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{
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ktime_t deadline = ktime_add_us(ktime_get(), 10000);
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if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
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return false;
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atomic_inc(&ring->adev->gpu_reset_counter);
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while (!dma_fence_is_signaled(fence) &&
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ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
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ring->funcs->soft_recovery(ring, vmid);
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return dma_fence_is_signaled(fence);
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}
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/*
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* Debugfs info
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||
|
|
*/
|
||
|
|
#if defined(CONFIG_DEBUG_FS)
|
||
|
|
|
||
|
|
/* Layout of file is 12 bytes consisting of
|
||
|
|
* - rptr
|
||
|
|
* - wptr
|
||
|
|
* - driver's copy of wptr
|
||
|
|
*
|
||
|
|
* followed by n-words of ring data
|
||
|
|
*/
|
||
|
|
static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
|
||
|
|
size_t size, loff_t *pos)
|
||
|
|
{
|
||
|
|
struct amdgpu_ring *ring = file_inode(f)->i_private;
|
||
|
|
int r, i;
|
||
|
|
uint32_t value, result, early[3];
|
||
|
|
|
||
|
|
if (*pos & 3 || size & 3)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
result = 0;
|
||
|
|
|
||
|
|
if (*pos < 12) {
|
||
|
|
early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
|
||
|
|
early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
|
||
|
|
early[2] = ring->wptr & ring->buf_mask;
|
||
|
|
for (i = *pos / 4; i < 3 && size; i++) {
|
||
|
|
r = put_user(early[i], (uint32_t *)buf);
|
||
|
|
if (r)
|
||
|
|
return r;
|
||
|
|
buf += 4;
|
||
|
|
result += 4;
|
||
|
|
size -= 4;
|
||
|
|
*pos += 4;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
while (size) {
|
||
|
|
if (*pos >= (ring->ring_size + 12))
|
||
|
|
return result;
|
||
|
|
|
||
|
|
value = ring->ring[(*pos - 12)/4];
|
||
|
|
r = put_user(value, (uint32_t *)buf);
|
||
|
|
if (r)
|
||
|
|
return r;
|
||
|
|
buf += 4;
|
||
|
|
result += 4;
|
||
|
|
size -= 4;
|
||
|
|
*pos += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct file_operations amdgpu_debugfs_ring_fops = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.read = amdgpu_debugfs_ring_read,
|
||
|
|
.llseek = default_llseek
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_ring *ring)
|
||
|
|
{
|
||
|
|
#if defined(CONFIG_DEBUG_FS)
|
||
|
|
struct drm_minor *minor = adev_to_drm(adev)->primary;
|
||
|
|
struct dentry *root = minor->debugfs_root;
|
||
|
|
char name[32];
|
||
|
|
|
||
|
|
sprintf(name, "amdgpu_ring_%s", ring->name);
|
||
|
|
debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, ring,
|
||
|
|
&amdgpu_debugfs_ring_fops,
|
||
|
|
ring->ring_size + 12);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_ring_test_helper - tests ring and set sched readiness status
|
||
|
|
*
|
||
|
|
* @ring: ring to try the recovery on
|
||
|
|
*
|
||
|
|
* Tests ring and set sched readiness status
|
||
|
|
*
|
||
|
|
* Returns 0 on success, error on failure.
|
||
|
|
*/
|
||
|
|
int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
|
||
|
|
{
|
||
|
|
struct amdgpu_device *adev = ring->adev;
|
||
|
|
int r;
|
||
|
|
|
||
|
|
r = amdgpu_ring_test_ring(ring);
|
||
|
|
if (r)
|
||
|
|
DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
|
||
|
|
ring->name, r);
|
||
|
|
else
|
||
|
|
DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
|
||
|
|
ring->name);
|
||
|
|
|
||
|
|
ring->sched.ready = !r;
|
||
|
|
return r;
|
||
|
|
}
|