73 lines
2.8 KiB
C
73 lines
2.8 KiB
C
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_ras.h"
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#include "amdgpu.h"
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#include "amdgpu_mca.h"
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#include "umc/umc_6_7_0_offset.h"
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#include "umc/umc_6_7_0_sh_mask.h"
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void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count)
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{
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uint64_t mc_status = RREG64_PCIE(mc_status_addr);
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if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count)
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{
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uint64_t mc_status = RREG64_PCIE(mc_status_addr);
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if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr)
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{
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WREG64_PCIE(mc_status_addr, 0x0ULL);
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}
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void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count));
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amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count));
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amdgpu_mca_reset_error_count(adev, mc_status_addr);
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}
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