297 lines
8.0 KiB
C
297 lines
8.0 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/dma-mapping.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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/**
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* amdgpu_ih_ring_init - initialize the IH state
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*
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* @adev: amdgpu_device pointer
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* @ih: ih ring to initialize
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* @ring_size: ring size to allocate
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* @use_bus_addr: true when we can use dma_alloc_coherent
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*
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* Initializes the IH state and allocates a buffer
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* for the IH ring buffer.
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* Returns 0 for success, errors for failure.
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*/
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int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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unsigned ring_size, bool use_bus_addr)
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{
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u32 rb_bufsz;
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int r;
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/* Align ring size */
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rb_bufsz = order_base_2(ring_size / 4);
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ring_size = (1 << rb_bufsz) * 4;
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ih->ring_size = ring_size;
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ih->ptr_mask = ih->ring_size - 1;
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ih->rptr = 0;
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ih->use_bus_addr = use_bus_addr;
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if (use_bus_addr) {
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dma_addr_t dma_addr;
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if (ih->ring)
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return 0;
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/* add 8 bytes for the rptr/wptr shadows and
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* add them to the end of the ring allocation.
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*/
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ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
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&dma_addr, GFP_KERNEL);
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if (ih->ring == NULL)
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return -ENOMEM;
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ih->gpu_addr = dma_addr;
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ih->wptr_addr = dma_addr + ih->ring_size;
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ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
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ih->rptr_addr = dma_addr + ih->ring_size + 4;
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ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
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} else {
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unsigned wptr_offs, rptr_offs;
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r = amdgpu_device_wb_get(adev, &wptr_offs);
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if (r)
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return r;
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r = amdgpu_device_wb_get(adev, &rptr_offs);
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if (r) {
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amdgpu_device_wb_free(adev, wptr_offs);
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return r;
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}
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r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT,
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&ih->ring_obj, &ih->gpu_addr,
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(void **)&ih->ring);
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if (r) {
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amdgpu_device_wb_free(adev, rptr_offs);
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amdgpu_device_wb_free(adev, wptr_offs);
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return r;
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}
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ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
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ih->wptr_cpu = &adev->wb.wb[wptr_offs];
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ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
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ih->rptr_cpu = &adev->wb.wb[rptr_offs];
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}
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init_waitqueue_head(&ih->wait_process);
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return 0;
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}
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/**
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* amdgpu_ih_ring_fini - tear down the IH state
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*
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* @adev: amdgpu_device pointer
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* @ih: ih ring to tear down
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*
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* Tears down the IH state and frees buffer
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* used for the IH ring buffer.
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*/
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void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
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{
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if (!ih->ring)
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return;
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if (ih->use_bus_addr) {
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/* add 8 bytes for the rptr/wptr shadows and
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* add them to the end of the ring allocation.
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*/
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dma_free_coherent(adev->dev, ih->ring_size + 8,
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(void *)ih->ring, ih->gpu_addr);
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ih->ring = NULL;
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} else {
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amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
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(void **)&ih->ring);
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amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
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amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
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}
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}
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/**
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* amdgpu_ih_ring_write - write IV to the ring buffer
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*
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* @ih: ih ring to write to
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* @iv: the iv to write
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* @num_dw: size of the iv in dw
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*
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* Writes an IV to the ring buffer using the CPU and increment the wptr.
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* Used for testing and delegating IVs to a software ring.
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*/
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void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
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unsigned int num_dw)
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{
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uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
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unsigned int i;
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for (i = 0; i < num_dw; ++i)
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ih->ring[wptr++] = cpu_to_le32(iv[i]);
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wptr <<= 2;
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wptr &= ih->ptr_mask;
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/* Only commit the new wptr if we don't overflow */
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if (wptr != READ_ONCE(ih->rptr)) {
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wmb();
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WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
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}
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}
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/**
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* amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to checkpoint
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*
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* @adev: amdgpu_device pointer
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* @ih: ih ring to process
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*
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* Used to ensure ring has processed IVs up to the checkpoint write pointer.
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*/
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int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih)
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{
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uint32_t checkpoint_wptr;
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uint64_t checkpoint_ts;
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long timeout = HZ;
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if (!ih->enabled || adev->shutdown)
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return -ENODEV;
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checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
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/* Order wptr with ring data. */
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rmb();
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checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
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return wait_event_interruptible_timeout(ih->wait_process,
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amdgpu_ih_ts_after(checkpoint_ts, ih->processed_timestamp) ||
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ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout);
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}
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/**
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* amdgpu_ih_process - interrupt handler
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*
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* @adev: amdgpu_device pointer
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* @ih: ih ring to process
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*
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* Interrupt hander (VI), walk the IH ring.
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* Returns irq process return code.
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*/
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int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
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{
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unsigned int count;
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u32 wptr;
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if (!ih->enabled || adev->shutdown)
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return IRQ_NONE;
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wptr = amdgpu_ih_get_wptr(adev, ih);
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restart_ih:
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count = AMDGPU_IH_MAX_NUM_IVS;
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DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
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/* Order reading of wptr vs. reading of IH ring data */
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rmb();
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while (ih->rptr != wptr && --count) {
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amdgpu_irq_dispatch(adev, ih);
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ih->rptr &= ih->ptr_mask;
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}
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amdgpu_ih_set_rptr(adev, ih);
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wake_up_all(&ih->wait_process);
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/* make sure wptr hasn't changed while processing */
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wptr = amdgpu_ih_get_wptr(adev, ih);
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if (wptr != ih->rptr)
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goto restart_ih;
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return IRQ_HANDLED;
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}
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/**
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* amdgpu_ih_decode_iv_helper - decode an interrupt vector
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*
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* @adev: amdgpu_device pointer
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* @ih: ih ring to process
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* @entry: IV entry
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*
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* Decodes the interrupt vector at the current rptr
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* position and also advance the position for for Vega10
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* and later GPUs.
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*/
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void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih,
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struct amdgpu_iv_entry *entry)
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{
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/* wptr/rptr are in bytes! */
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u32 ring_index = ih->rptr >> 2;
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uint32_t dw[8];
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dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
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dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
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dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
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dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
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dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
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dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
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dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
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dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
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entry->client_id = dw[0] & 0xff;
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entry->src_id = (dw[0] >> 8) & 0xff;
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entry->ring_id = (dw[0] >> 16) & 0xff;
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entry->vmid = (dw[0] >> 24) & 0xf;
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entry->vmid_src = (dw[0] >> 31);
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entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
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entry->timestamp_src = dw[2] >> 31;
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entry->pasid = dw[3] & 0xffff;
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entry->pasid_src = dw[3] >> 31;
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entry->src_data[0] = dw[4];
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entry->src_data[1] = dw[5];
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entry->src_data[2] = dw[6];
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entry->src_data[3] = dw[7];
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/* wptr/rptr are in bytes! */
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ih->rptr += 32;
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}
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uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
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signed int offset)
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{
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uint32_t iv_size = 32;
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uint32_t ring_index;
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uint32_t dw1, dw2;
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rptr += iv_size * offset;
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ring_index = (rptr & ih->ptr_mask) >> 2;
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dw1 = le32_to_cpu(ih->ring[ring_index + 1]);
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dw2 = le32_to_cpu(ih->ring[ring_index + 2]);
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return dw1 | ((u64)(dw2 & 0xffff) << 32);
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}
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