341 lines
12 KiB
C
341 lines
12 KiB
C
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#ifndef __AMDGPU_GMC_H__
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#define __AMDGPU_GMC_H__
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#include <linux/types.h>
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#include "amdgpu_irq.h"
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#include "amdgpu_ras.h"
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/* VA hole for 48bit addresses on Vega10 */
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#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
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#define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
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/*
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* Hardware is programmed as if the hole doesn't exists with start and end
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* address values.
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*
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* This mask is used to remove the upper 16bits of the VA and so come up with
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* the linear addr value.
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*/
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#define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
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/*
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* Ring size as power of two for the log of recent faults.
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*/
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#define AMDGPU_GMC_FAULT_RING_ORDER 8
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#define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER)
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/*
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* Hash size as power of two for the log of recent faults
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*/
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#define AMDGPU_GMC_FAULT_HASH_ORDER 8
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#define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
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/*
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* Number of IH timestamp ticks until a fault is considered handled
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*/
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#define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL
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struct firmware;
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/*
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* GMC page fault information
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*/
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struct amdgpu_gmc_fault {
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uint64_t timestamp:48;
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uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
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atomic64_t key;
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};
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/*
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* VMHUB structures, functions & helpers
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*/
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struct amdgpu_vmhub_funcs {
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void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
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uint32_t status);
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uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
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};
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struct amdgpu_vmhub {
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uint32_t ctx0_ptb_addr_lo32;
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uint32_t ctx0_ptb_addr_hi32;
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uint32_t vm_inv_eng0_sem;
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uint32_t vm_inv_eng0_req;
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uint32_t vm_inv_eng0_ack;
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uint32_t vm_context0_cntl;
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uint32_t vm_l2_pro_fault_status;
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uint32_t vm_l2_pro_fault_cntl;
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/*
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* store the register distances between two continuous context domain
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* and invalidation engine.
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*/
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uint32_t ctx_distance;
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uint32_t ctx_addr_distance; /* include LO32/HI32 */
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uint32_t eng_distance;
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uint32_t eng_addr_distance; /* include LO32/HI32 */
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uint32_t vm_cntx_cntl_vm_fault;
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const struct amdgpu_vmhub_funcs *vmhub_funcs;
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};
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/*
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* GPU MC structures, functions & helpers
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*/
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struct amdgpu_gmc_funcs {
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/* flush the vm tlb via mmio */
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void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t vmhub, uint32_t flush_type);
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/* flush the vm tlb via pasid */
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int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
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uint32_t flush_type, bool all_hub);
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/* flush the vm tlb via ring */
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uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
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uint64_t pd_addr);
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/* Change the VMID -> PASID mapping */
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void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
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unsigned pasid);
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/* enable/disable PRT support */
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void (*set_prt)(struct amdgpu_device *adev, bool enable);
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/* map mtype to hardware flags */
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uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
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/* get the pde for a given mc addr */
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void (*get_vm_pde)(struct amdgpu_device *adev, int level,
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u64 *dst, u64 *flags);
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/* get the pte flags to use for a BO VA mapping */
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void (*get_vm_pte)(struct amdgpu_device *adev,
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struct amdgpu_bo_va_mapping *mapping,
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uint64_t *flags);
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/* get the amount of memory used by the vbios for pre-OS console */
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unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
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};
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struct amdgpu_xgmi_ras {
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struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_xgmi {
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/* from psp */
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u64 node_id;
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u64 hive_id;
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/* fixed per family */
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u64 node_segment_size;
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/* physical node (0-3) */
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unsigned physical_node_id;
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/* number of nodes (0-4) */
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unsigned num_physical_nodes;
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/* gpu list in the same hive */
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struct list_head head;
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bool supported;
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struct ras_common_if *ras_if;
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bool connected_to_cpu;
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bool pending_reset;
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struct amdgpu_xgmi_ras *ras;
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};
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struct amdgpu_gmc {
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/* FB's physical address in MMIO space (for CPU to
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* map FB). This is different compared to the agp/
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* gart/vram_start/end field as the later is from
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* GPU's view and aper_base is from CPU's view.
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*/
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resource_size_t aper_size;
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resource_size_t aper_base;
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/* for some chips with <= 32MB we need to lie
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* about vram size near mc fb location */
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u64 mc_vram_size;
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u64 visible_vram_size;
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/* AGP aperture start and end in MC address space
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* Driver find a hole in the MC address space
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* to place AGP by setting MC_VM_AGP_BOT/TOP registers
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* Under VMID0, logical address == MC address. AGP
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* aperture maps to physical bus or IOVA addressed.
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* AGP aperture is used to simulate FB in ZFB case.
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* AGP aperture is also used for page table in system
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* memory (mainly for APU).
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*
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*/
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u64 agp_size;
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u64 agp_start;
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u64 agp_end;
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/* GART aperture start and end in MC address space
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* Driver find a hole in the MC address space
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* to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
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* registers
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* Under VMID0, logical address inside GART aperture will
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* be translated through gpuvm gart page table to access
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* paged system memory
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*/
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u64 gart_size;
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u64 gart_start;
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u64 gart_end;
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/* Frame buffer aperture of this GPU device. Different from
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* fb_start (see below), this only covers the local GPU device.
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* If driver uses FB aperture to access FB, driver get fb_start from
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* MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start
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* of this local device by adding an offset inside the XGMI hive.
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* If driver uses GART table for VMID0 FB access, driver finds a hole in
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* VMID0's virtual address space to place the SYSVM aperture inside
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* which the first part is vram and the second part is gart (covering
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* system ram).
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*/
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u64 vram_start;
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u64 vram_end;
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/* FB region , it's same as local vram region in single GPU, in XGMI
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* configuration, this region covers all GPUs in the same hive ,
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* each GPU in the hive has the same view of this FB region .
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* GPU0's vram starts at offset (0 * segment size) ,
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* GPU1 starts at offset (1 * segment size), etc.
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*/
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u64 fb_start;
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u64 fb_end;
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unsigned vram_width;
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u64 real_vram_size;
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int vram_mtrr;
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u64 mc_mask;
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const struct firmware *fw; /* MC firmware */
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uint32_t fw_version;
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struct amdgpu_irq_src vm_fault;
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uint32_t vram_type;
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uint8_t vram_vendor;
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uint32_t srbm_soft_reset;
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bool prt_warning;
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uint32_t sdpif_register;
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/* apertures */
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u64 shared_aperture_start;
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u64 shared_aperture_end;
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u64 private_aperture_start;
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u64 private_aperture_end;
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/* protects concurrent invalidation */
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spinlock_t invalidate_lock;
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bool translate_further;
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struct kfd_vm_fault_info *vm_fault_info;
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atomic_t vm_fault_info_updated;
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struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
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struct {
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uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
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} fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
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uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
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bool tmz_enabled;
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const struct amdgpu_gmc_funcs *gmc_funcs;
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struct amdgpu_xgmi xgmi;
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struct amdgpu_irq_src ecc_irq;
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int noretry;
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uint32_t vmid0_page_table_block_size;
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uint32_t vmid0_page_table_depth;
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struct amdgpu_bo *pdb0_bo;
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/* CPU kmapped address of pdb0*/
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void *ptr_pdb0;
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};
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#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
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#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
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((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
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((adev), (pasid), (type), (allhub)))
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#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
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#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
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#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
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#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
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#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
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#define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
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/**
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* amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
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*
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* @adev: amdgpu_device pointer
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*
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* Returns:
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* True if full VRAM is visible through the BAR
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*/
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static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
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{
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WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
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return (gmc->real_vram_size == gmc->visible_vram_size);
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}
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/**
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* amdgpu_gmc_sign_extend - sign extend the given gmc address
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*
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* @addr: address to extend
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*/
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static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
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{
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if (addr >= AMDGPU_GMC_HOLE_START)
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addr |= AMDGPU_GMC_HOLE_END;
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return addr;
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}
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int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
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void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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uint64_t *addr, uint64_t *flags);
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int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
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uint32_t gpu_page_idx, uint64_t addr,
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uint64_t flags);
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uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
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uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
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void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc);
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void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
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u64 base);
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void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc);
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void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
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struct amdgpu_gmc *mc);
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bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih, uint64_t addr,
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uint16_t pasid, uint64_t timestamp);
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void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
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uint16_t pasid);
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int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev);
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int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
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void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
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int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
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extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
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extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev);
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extern void
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amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
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bool enable);
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void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
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void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
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uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
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uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
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uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
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int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
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#endif
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