400 lines
9.0 KiB
C
400 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* System Control and Management Interface (SCMI) Clock Protocol
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*
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* Copyright (C) 2018-2021 ARM Ltd.
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*/
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#include <linux/module.h>
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#include <linux/sort.h>
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#include "common.h"
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enum scmi_clock_protocol_cmd {
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CLOCK_ATTRIBUTES = 0x3,
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CLOCK_DESCRIBE_RATES = 0x4,
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CLOCK_RATE_SET = 0x5,
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CLOCK_RATE_GET = 0x6,
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CLOCK_CONFIG_SET = 0x7,
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};
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struct scmi_msg_resp_clock_protocol_attributes {
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__le16 num_clocks;
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u8 max_async_req;
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u8 reserved;
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};
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struct scmi_msg_resp_clock_attributes {
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__le32 attributes;
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#define CLOCK_ENABLE BIT(0)
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u8 name[SCMI_MAX_STR_SIZE];
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__le32 clock_enable_latency;
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};
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struct scmi_clock_set_config {
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__le32 id;
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__le32 attributes;
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};
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struct scmi_msg_clock_describe_rates {
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__le32 id;
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__le32 rate_index;
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};
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struct scmi_msg_resp_clock_describe_rates {
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__le32 num_rates_flags;
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#define NUM_RETURNED(x) ((x) & 0xfff)
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#define RATE_DISCRETE(x) !((x) & BIT(12))
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#define NUM_REMAINING(x) ((x) >> 16)
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struct {
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__le32 value_low;
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__le32 value_high;
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} rate[];
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#define RATE_TO_U64(X) \
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({ \
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typeof(X) x = (X); \
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le32_to_cpu((x).value_low) | (u64)le32_to_cpu((x).value_high) << 32; \
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})
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};
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struct scmi_clock_set_rate {
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__le32 flags;
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#define CLOCK_SET_ASYNC BIT(0)
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#define CLOCK_SET_IGNORE_RESP BIT(1)
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#define CLOCK_SET_ROUND_UP BIT(2)
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#define CLOCK_SET_ROUND_AUTO BIT(3)
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__le32 id;
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__le32 value_low;
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__le32 value_high;
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};
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struct clock_info {
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u32 version;
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int num_clocks;
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int max_async_req;
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atomic_t cur_async_req;
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struct scmi_clock_info *clk;
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};
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static int
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scmi_clock_protocol_attributes_get(const struct scmi_protocol_handle *ph,
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struct clock_info *ci)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_msg_resp_clock_protocol_attributes *attr;
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ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES,
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0, sizeof(*attr), &t);
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if (ret)
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return ret;
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attr = t->rx.buf;
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ret = ph->xops->do_xfer(ph, t);
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if (!ret) {
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ci->num_clocks = le16_to_cpu(attr->num_clocks);
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ci->max_async_req = attr->max_async_req;
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}
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
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u32 clk_id, struct scmi_clock_info *clk)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_msg_resp_clock_attributes *attr;
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ret = ph->xops->xfer_get_init(ph, CLOCK_ATTRIBUTES,
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sizeof(clk_id), sizeof(*attr), &t);
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if (ret)
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return ret;
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put_unaligned_le32(clk_id, t->tx.buf);
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attr = t->rx.buf;
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ret = ph->xops->do_xfer(ph, t);
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if (!ret) {
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strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE);
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/* Is optional field clock_enable_latency provided ? */
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if (t->rx.len == sizeof(*attr))
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clk->enable_latency =
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le32_to_cpu(attr->clock_enable_latency);
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} else {
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clk->name[0] = '\0';
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}
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int rate_cmp_func(const void *_r1, const void *_r2)
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{
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const u64 *r1 = _r1, *r2 = _r2;
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if (*r1 < *r2)
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return -1;
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else if (*r1 == *r2)
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return 0;
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else
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return 1;
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}
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static int
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scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
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struct scmi_clock_info *clk)
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{
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u64 *rate = NULL;
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int ret, cnt;
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bool rate_discrete = false;
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u32 tot_rate_cnt = 0, rates_flag;
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u16 num_returned, num_remaining;
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struct scmi_xfer *t;
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struct scmi_msg_clock_describe_rates *clk_desc;
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struct scmi_msg_resp_clock_describe_rates *rlist;
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ret = ph->xops->xfer_get_init(ph, CLOCK_DESCRIBE_RATES,
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sizeof(*clk_desc), 0, &t);
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if (ret)
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return ret;
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clk_desc = t->tx.buf;
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rlist = t->rx.buf;
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do {
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clk_desc->id = cpu_to_le32(clk_id);
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/* Set the number of rates to be skipped/already read */
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clk_desc->rate_index = cpu_to_le32(tot_rate_cnt);
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ret = ph->xops->do_xfer(ph, t);
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if (ret)
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goto err;
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rates_flag = le32_to_cpu(rlist->num_rates_flags);
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num_remaining = NUM_REMAINING(rates_flag);
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rate_discrete = RATE_DISCRETE(rates_flag);
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num_returned = NUM_RETURNED(rates_flag);
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if (tot_rate_cnt + num_returned > SCMI_MAX_NUM_RATES) {
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dev_err(ph->dev, "No. of rates > MAX_NUM_RATES");
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break;
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}
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if (!rate_discrete) {
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clk->range.min_rate = RATE_TO_U64(rlist->rate[0]);
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clk->range.max_rate = RATE_TO_U64(rlist->rate[1]);
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clk->range.step_size = RATE_TO_U64(rlist->rate[2]);
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dev_dbg(ph->dev, "Min %llu Max %llu Step %llu Hz\n",
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clk->range.min_rate, clk->range.max_rate,
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clk->range.step_size);
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break;
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}
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rate = &clk->list.rates[tot_rate_cnt];
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for (cnt = 0; cnt < num_returned; cnt++, rate++) {
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*rate = RATE_TO_U64(rlist->rate[cnt]);
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dev_dbg(ph->dev, "Rate %llu Hz\n", *rate);
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}
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tot_rate_cnt += num_returned;
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ph->xops->reset_rx_to_maxsz(ph, t);
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/*
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* check for both returned and remaining to avoid infinite
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* loop due to buggy firmware
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*/
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} while (num_returned && num_remaining);
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if (rate_discrete && rate) {
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clk->list.num_rates = tot_rate_cnt;
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sort(clk->list.rates, tot_rate_cnt, sizeof(*rate),
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rate_cmp_func, NULL);
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}
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clk->rate_discrete = rate_discrete;
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err:
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int
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scmi_clock_rate_get(const struct scmi_protocol_handle *ph,
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u32 clk_id, u64 *value)
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{
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int ret;
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struct scmi_xfer *t;
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ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_GET,
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sizeof(__le32), sizeof(u64), &t);
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if (ret)
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return ret;
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put_unaligned_le32(clk_id, t->tx.buf);
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ret = ph->xops->do_xfer(ph, t);
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if (!ret)
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*value = get_unaligned_le64(t->rx.buf);
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph,
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u32 clk_id, u64 rate)
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{
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int ret;
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u32 flags = 0;
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struct scmi_xfer *t;
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struct scmi_clock_set_rate *cfg;
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struct clock_info *ci = ph->get_priv(ph);
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ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_SET, sizeof(*cfg), 0, &t);
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if (ret)
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return ret;
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if (ci->max_async_req &&
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atomic_inc_return(&ci->cur_async_req) < ci->max_async_req)
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flags |= CLOCK_SET_ASYNC;
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cfg = t->tx.buf;
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cfg->flags = cpu_to_le32(flags);
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cfg->id = cpu_to_le32(clk_id);
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cfg->value_low = cpu_to_le32(rate & 0xffffffff);
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cfg->value_high = cpu_to_le32(rate >> 32);
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if (flags & CLOCK_SET_ASYNC)
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ret = ph->xops->do_xfer_with_response(ph, t);
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else
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ret = ph->xops->do_xfer(ph, t);
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if (ci->max_async_req)
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atomic_dec(&ci->cur_async_req);
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int
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scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id,
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u32 config, bool atomic)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_clock_set_config *cfg;
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ret = ph->xops->xfer_get_init(ph, CLOCK_CONFIG_SET,
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sizeof(*cfg), 0, &t);
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if (ret)
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return ret;
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t->hdr.poll_completion = atomic;
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cfg = t->tx.buf;
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cfg->id = cpu_to_le32(clk_id);
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cfg->attributes = cpu_to_le32(config);
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ret = ph->xops->do_xfer(ph, t);
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ph->xops->xfer_put(ph, t);
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return ret;
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}
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static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 clk_id)
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{
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return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, false);
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}
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static int scmi_clock_disable(const struct scmi_protocol_handle *ph, u32 clk_id)
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{
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return scmi_clock_config_set(ph, clk_id, 0, false);
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}
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static int scmi_clock_enable_atomic(const struct scmi_protocol_handle *ph,
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u32 clk_id)
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{
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return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, true);
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}
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static int scmi_clock_disable_atomic(const struct scmi_protocol_handle *ph,
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u32 clk_id)
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{
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return scmi_clock_config_set(ph, clk_id, 0, true);
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}
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static int scmi_clock_count_get(const struct scmi_protocol_handle *ph)
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{
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struct clock_info *ci = ph->get_priv(ph);
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return ci->num_clocks;
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}
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static const struct scmi_clock_info *
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scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id)
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{
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struct clock_info *ci = ph->get_priv(ph);
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struct scmi_clock_info *clk = ci->clk + clk_id;
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if (!clk->name[0])
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return NULL;
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return clk;
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}
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static const struct scmi_clk_proto_ops clk_proto_ops = {
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.count_get = scmi_clock_count_get,
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.info_get = scmi_clock_info_get,
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.rate_get = scmi_clock_rate_get,
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.rate_set = scmi_clock_rate_set,
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.enable = scmi_clock_enable,
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.disable = scmi_clock_disable,
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.enable_atomic = scmi_clock_enable_atomic,
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.disable_atomic = scmi_clock_disable_atomic,
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};
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static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
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{
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u32 version;
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int clkid, ret;
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struct clock_info *cinfo;
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ph->xops->version_get(ph, &version);
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dev_dbg(ph->dev, "Clock Version %d.%d\n",
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PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
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cinfo = devm_kzalloc(ph->dev, sizeof(*cinfo), GFP_KERNEL);
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if (!cinfo)
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return -ENOMEM;
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scmi_clock_protocol_attributes_get(ph, cinfo);
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|
||
|
|
cinfo->clk = devm_kcalloc(ph->dev, cinfo->num_clocks,
|
||
|
|
sizeof(*cinfo->clk), GFP_KERNEL);
|
||
|
|
if (!cinfo->clk)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
|
||
|
|
struct scmi_clock_info *clk = cinfo->clk + clkid;
|
||
|
|
|
||
|
|
ret = scmi_clock_attributes_get(ph, clkid, clk);
|
||
|
|
if (!ret)
|
||
|
|
scmi_clock_describe_rates_get(ph, clkid, clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
cinfo->version = version;
|
||
|
|
return ph->set_priv(ph, cinfo);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct scmi_protocol scmi_clock = {
|
||
|
|
.id = SCMI_PROTOCOL_CLOCK,
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.instance_init = &scmi_clock_protocol_init,
|
||
|
|
.ops = &clk_proto_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(clock, scmi_clock)
|