446 lines
13 KiB
C
446 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MMP Audio Clock Controller driver
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*
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* Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/marvell,mmp2-audio.h>
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/* Audio Controller Registers */
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#define SSPA_AUD_CTRL 0x04
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#define SSPA_AUD_PLL_CTRL0 0x08
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#define SSPA_AUD_PLL_CTRL1 0x0c
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/* SSPA Audio Control Register */
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#define SSPA_AUD_CTRL_SYSCLK_SHIFT 0
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#define SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT 1
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#define SSPA_AUD_CTRL_SSPA0_MUX_SHIFT 7
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#define SSPA_AUD_CTRL_SSPA0_SHIFT 8
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#define SSPA_AUD_CTRL_SSPA0_DIV_SHIFT 9
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#define SSPA_AUD_CTRL_SSPA1_SHIFT 16
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#define SSPA_AUD_CTRL_SSPA1_DIV_SHIFT 17
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#define SSPA_AUD_CTRL_SSPA1_MUX_SHIFT 23
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#define SSPA_AUD_CTRL_DIV_MASK 0x7e
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/* SSPA Audio PLL Control 0 Register */
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#define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK (0x7 << 28)
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#define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(x) ((x) << 28)
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#define SSPA_AUD_PLL_CTRL0_FRACT_MASK (0xfffff << 8)
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#define SSPA_AUD_PLL_CTRL0_FRACT(x) ((x) << 8)
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#define SSPA_AUD_PLL_CTRL0_ENA_DITHER (1 << 7)
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#define SSPA_AUD_PLL_CTRL0_ICP_2UA (0 << 5)
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#define SSPA_AUD_PLL_CTRL0_ICP_5UA (1 << 5)
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#define SSPA_AUD_PLL_CTRL0_ICP_7UA (2 << 5)
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#define SSPA_AUD_PLL_CTRL0_ICP_10UA (3 << 5)
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#define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK (0x3 << 3)
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#define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(x) ((x) << 3)
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#define SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK (0x1 << 2)
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#define SSPA_AUD_PLL_CTRL0_DIV_MCLK(x) ((x) << 2)
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#define SSPA_AUD_PLL_CTRL0_PD_OVPROT_DIS (1 << 1)
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#define SSPA_AUD_PLL_CTRL0_PU (1 << 0)
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/* SSPA Audio PLL Control 1 Register */
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#define SSPA_AUD_PLL_CTRL1_SEL_FAST_CLK (1 << 24)
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#define SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK (1 << 11)
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#define SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL (1 << 11)
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#define SSPA_AUD_PLL_CTRL1_CLK_SEL_VCXO (0 << 11)
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#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
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#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0)
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struct mmp2_audio_clk {
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void __iomem *mmio_base;
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struct clk_hw audio_pll_hw;
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struct clk_mux sspa_mux;
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struct clk_mux sspa1_mux;
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struct clk_divider sysclk_div;
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struct clk_divider sspa0_div;
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struct clk_divider sspa1_div;
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struct clk_gate sysclk_gate;
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struct clk_gate sspa0_gate;
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struct clk_gate sspa1_gate;
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u32 aud_ctrl;
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u32 aud_pll_ctrl0;
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u32 aud_pll_ctrl1;
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spinlock_t lock;
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/* Must be last */
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struct clk_hw_onecell_data clk_data;
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};
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static const struct {
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unsigned long parent_rate;
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unsigned long freq_vco;
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unsigned char mclk;
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unsigned char fbcclk;
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unsigned short fract;
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} predivs[] = {
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{ 26000000, 135475200, 0, 0, 0x8a18 },
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{ 26000000, 147456000, 0, 1, 0x0da1 },
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{ 38400000, 135475200, 1, 2, 0x8208 },
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{ 38400000, 147456000, 1, 3, 0xaaaa },
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};
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static const struct {
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unsigned char divisor;
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unsigned char modulo;
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unsigned char pattern;
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} postdivs[] = {
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{ 1, 3, 0, },
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{ 2, 5, 0, },
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{ 4, 0, 0, },
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{ 6, 1, 1, },
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{ 8, 1, 0, },
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{ 9, 1, 2, },
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{ 12, 2, 1, },
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{ 16, 2, 0, },
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{ 18, 2, 2, },
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{ 24, 4, 1, },
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{ 36, 4, 2, },
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{ 48, 6, 1, },
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{ 72, 6, 2, },
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};
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static unsigned long audio_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
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unsigned int prediv;
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unsigned int postdiv;
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u32 aud_pll_ctrl0;
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u32 aud_pll_ctrl1;
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aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
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aud_pll_ctrl0 &= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK |
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SSPA_AUD_PLL_CTRL0_FRACT_MASK |
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SSPA_AUD_PLL_CTRL0_ENA_DITHER |
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SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK |
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SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK |
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SSPA_AUD_PLL_CTRL0_PU;
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aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
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aud_pll_ctrl1 &= SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK |
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SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK;
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for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
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if (predivs[prediv].parent_rate != parent_rate)
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continue;
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for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
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unsigned long freq;
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u32 val;
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val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
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val |= SSPA_AUD_PLL_CTRL0_PU;
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val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
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val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
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val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
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val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
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if (val != aud_pll_ctrl0)
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continue;
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val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
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val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
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if (val != aud_pll_ctrl1)
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continue;
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freq = predivs[prediv].freq_vco;
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freq /= postdivs[postdiv].divisor;
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return freq;
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}
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}
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return 0;
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}
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static long audio_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int prediv;
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unsigned int postdiv;
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long rounded = 0;
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for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
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if (predivs[prediv].parent_rate != *parent_rate)
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continue;
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for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
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long freq = predivs[prediv].freq_vco;
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freq /= postdivs[postdiv].divisor;
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if (freq == rate)
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return rate;
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if (freq < rate)
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continue;
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if (rounded && freq > rounded)
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continue;
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rounded = freq;
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}
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}
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return rounded;
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}
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static int audio_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
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unsigned int prediv;
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unsigned int postdiv;
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unsigned long val;
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for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
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if (predivs[prediv].parent_rate != parent_rate)
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continue;
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for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
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if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco)
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continue;
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val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
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val |= SSPA_AUD_PLL_CTRL0_PU;
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val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
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val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
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val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
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val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
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writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
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val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
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val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
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writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
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return 0;
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}
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}
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return -ERANGE;
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}
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static const struct clk_ops audio_pll_ops = {
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.recalc_rate = audio_pll_recalc_rate,
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.round_rate = audio_pll_round_rate,
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.set_rate = audio_pll_set_rate,
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};
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static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
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{
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const struct clk_parent_data sspa_mux_parents[] = {
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{ .hw = &priv->audio_pll_hw },
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{ .fw_name = "i2s0" },
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};
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const struct clk_parent_data sspa1_mux_parents[] = {
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{ .hw = &priv->audio_pll_hw },
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{ .fw_name = "i2s1" },
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};
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int ret;
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priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll",
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"vctcxo", &audio_pll_ops,
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CLK_SET_RATE_PARENT);
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ret = devm_clk_hw_register(dev, &priv->audio_pll_hw);
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if (ret)
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return ret;
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priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux",
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sspa_mux_parents, &clk_mux_ops,
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CLK_SET_RATE_PARENT);
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priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sspa_mux.mask = 1;
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priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT;
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ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw);
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if (ret)
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return ret;
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priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
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&priv->sspa_mux.hw, &clk_divider_ops,
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CLK_SET_RATE_PARENT);
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priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT;
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priv->sysclk_div.width = 6;
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priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
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priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
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priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
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ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw);
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if (ret)
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return ret;
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priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
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&priv->sysclk_div.hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT;
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ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw);
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if (ret)
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return ret;
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priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
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&priv->sspa_mux.hw, &clk_divider_ops, 0);
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priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT;
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priv->sspa0_div.width = 6;
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priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
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priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
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priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
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ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw);
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if (ret)
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return ret;
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priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
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&priv->sspa0_div.hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT;
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ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw);
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if (ret)
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return ret;
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priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux",
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sspa1_mux_parents, &clk_mux_ops,
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CLK_SET_RATE_PARENT);
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priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
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priv->sspa1_mux.mask = 1;
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priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT;
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ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw);
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if (ret)
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return ret;
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priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
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&priv->sspa1_mux.hw, &clk_divider_ops, 0);
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priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
|
||
|
|
priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT;
|
||
|
|
priv->sspa1_div.width = 6;
|
||
|
|
priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
|
||
|
|
priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
|
||
|
|
priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
|
||
|
|
ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
|
||
|
|
&priv->sspa1_div.hw, &clk_gate_ops,
|
||
|
|
CLK_SET_RATE_PARENT);
|
||
|
|
priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
|
||
|
|
priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT;
|
||
|
|
ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
|
||
|
|
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
|
||
|
|
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
|
||
|
|
priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS;
|
||
|
|
|
||
|
|
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||
|
|
&priv->clk_data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mmp2_audio_clk_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct mmp2_audio_clk *priv;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
priv = devm_kzalloc(&pdev->dev,
|
||
|
|
struct_size(priv, clk_data.hws,
|
||
|
|
MMP2_CLK_AUDIO_NR_CLKS),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!priv)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
spin_lock_init(&priv->lock);
|
||
|
|
platform_set_drvdata(pdev, priv);
|
||
|
|
|
||
|
|
priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);
|
||
|
|
if (IS_ERR(priv->mmio_base))
|
||
|
|
return PTR_ERR(priv->mmio_base);
|
||
|
|
|
||
|
|
pm_runtime_enable(&pdev->dev);
|
||
|
|
ret = pm_clk_create(&pdev->dev);
|
||
|
|
if (ret)
|
||
|
|
goto disable_pm_runtime;
|
||
|
|
|
||
|
|
ret = pm_clk_add(&pdev->dev, "audio");
|
||
|
|
if (ret)
|
||
|
|
goto destroy_pm_clk;
|
||
|
|
|
||
|
|
ret = register_clocks(priv, &pdev->dev);
|
||
|
|
if (ret)
|
||
|
|
goto destroy_pm_clk;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
destroy_pm_clk:
|
||
|
|
pm_clk_destroy(&pdev->dev);
|
||
|
|
disable_pm_runtime:
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mmp2_audio_clk_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
pm_clk_destroy(&pdev->dev);
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM
|
||
|
|
static int mmp2_audio_clk_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);
|
||
|
|
priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
|
||
|
|
priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
|
||
|
|
pm_clk_suspend(dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mmp2_audio_clk_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
pm_clk_resume(dev);
|
||
|
|
writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
|
||
|
|
writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
|
||
|
|
writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops mmp2_audio_clk_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(mmp2_audio_clk_suspend, mmp2_audio_clk_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id mmp2_audio_clk_of_match[] = {
|
||
|
|
{ .compatible = "marvell,mmp2-audio-clock" },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(of, mmp2_audio_clk_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver mmp2_audio_clk_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "mmp2-audio-clock",
|
||
|
|
.of_match_table = of_match_ptr(mmp2_audio_clk_of_match),
|
||
|
|
.pm = &mmp2_audio_clk_pm_ops,
|
||
|
|
},
|
||
|
|
.probe = mmp2_audio_clk_probe,
|
||
|
|
.remove = mmp2_audio_clk_remove,
|
||
|
|
};
|
||
|
|
module_platform_driver(mmp2_audio_clk_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
|
||
|
|
MODULE_DESCRIPTION("Clock driver for MMP2 Audio subsystem");
|
||
|
|
MODULE_LICENSE("GPL");
|