103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-mux.h"
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#include "clk-pll.h"
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#include <dt-bindings/clock/mt7986-clk.h>
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#include <linux/clk.h>
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#define MT7986_PLL_FMAX (2500UL * MHZ)
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#define CON0_MT7986_RST_BAR BIT(27)
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#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
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_div_table, _parent_name) \
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{ \
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.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, .flags = _flags, \
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.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
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.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, .div_table = _div_table, \
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.parent_name = _parent_name, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
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_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
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PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
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"clkxtal")
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
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0x0200, 4, 0, 0x0204, 0),
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PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
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0x0210, 4, 0, 0x0214, 0),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
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0x0220, 4, 0, 0x0224, 0),
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PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
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0x0230, 4, 0, 0x0234, 0),
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PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
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32, 0x0240, 4, 0, 0x0244, 0),
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PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
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0x0250, 4, 0, 0x0254, 0),
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PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
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4, 0, 0x0264, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
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0x0278, 4, 0, 0x027c, 0),
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};
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static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
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{ .compatible = "mediatek,mt7986-apmixedsys", },
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{}
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};
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static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
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if (!clk_data)
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return -ENOMEM;
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mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r) {
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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goto free_apmixed_data;
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}
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return r;
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static struct platform_driver clk_mt7986_apmixed_drv = {
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.probe = clk_mt7986_apmixed_probe,
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.driver = {
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.name = "clk-mt7986-apmixed",
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.of_match_table = of_match_clk_mt7986_apmixed,
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},
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};
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builtin_platform_driver(clk_mt7986_apmixed_drv);
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