305 lines
9.5 KiB
C
305 lines
9.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*
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*/
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#ifndef _MHI_COMMON_H
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#define _MHI_COMMON_H
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#include <linux/bitfield.h>
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#include <linux/mhi.h>
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/* MHI registers */
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#define MHIREGLEN 0x00
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#define MHIVER 0x08
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#define MHICFG 0x10
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#define CHDBOFF 0x18
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#define ERDBOFF 0x20
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#define BHIOFF 0x28
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#define BHIEOFF 0x2c
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#define DEBUGOFF 0x30
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#define MHICTRL 0x38
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#define MHISTATUS 0x48
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#define CCABAP_LOWER 0x58
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#define CCABAP_HIGHER 0x5c
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#define ECABAP_LOWER 0x60
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#define ECABAP_HIGHER 0x64
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#define CRCBAP_LOWER 0x68
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#define CRCBAP_HIGHER 0x6c
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#define CRDB_LOWER 0x70
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#define CRDB_HIGHER 0x74
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#define MHICTRLBASE_LOWER 0x80
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#define MHICTRLBASE_HIGHER 0x84
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#define MHICTRLLIMIT_LOWER 0x88
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#define MHICTRLLIMIT_HIGHER 0x8c
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#define MHIDATABASE_LOWER 0x98
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#define MHIDATABASE_HIGHER 0x9c
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#define MHIDATALIMIT_LOWER 0xa0
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#define MHIDATALIMIT_HIGHER 0xa4
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/* MHI BHI registers */
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#define BHI_BHIVERSION_MINOR 0x00
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#define BHI_BHIVERSION_MAJOR 0x04
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#define BHI_IMGADDR_LOW 0x08
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#define BHI_IMGADDR_HIGH 0x0c
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#define BHI_IMGSIZE 0x10
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#define BHI_RSVD1 0x14
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#define BHI_IMGTXDB 0x18
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#define BHI_RSVD2 0x1c
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#define BHI_INTVEC 0x20
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#define BHI_RSVD3 0x24
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#define BHI_EXECENV 0x28
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#define BHI_STATUS 0x2c
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#define BHI_ERRCODE 0x30
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#define BHI_ERRDBG1 0x34
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#define BHI_ERRDBG2 0x38
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#define BHI_ERRDBG3 0x3c
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#define BHI_SERIALNU 0x40
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#define BHI_SBLANTIROLLVER 0x44
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#define BHI_NUMSEG 0x48
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#define BHI_MSMHWID(n) (0x4c + (0x4 * (n)))
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#define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n)))
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#define BHI_RSVD5 0xc4
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/* BHI register bits */
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#define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
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#define BHI_TXDB_SEQNUM_SHFT 0
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#define BHI_STATUS_MASK GENMASK(31, 30)
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#define BHI_STATUS_ERROR 0x03
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#define BHI_STATUS_SUCCESS 0x02
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#define BHI_STATUS_RESET 0x00
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/* MHI BHIE registers */
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#define BHIE_MSMSOCID_OFFS 0x00
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#define BHIE_TXVECADDR_LOW_OFFS 0x2c
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#define BHIE_TXVECADDR_HIGH_OFFS 0x30
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#define BHIE_TXVECSIZE_OFFS 0x34
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#define BHIE_TXVECDB_OFFS 0x3c
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#define BHIE_TXVECSTATUS_OFFS 0x44
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#define BHIE_RXVECADDR_LOW_OFFS 0x60
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#define BHIE_RXVECADDR_HIGH_OFFS 0x64
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#define BHIE_RXVECSIZE_OFFS 0x68
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#define BHIE_RXVECDB_OFFS 0x70
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#define BHIE_RXVECSTATUS_OFFS 0x78
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/* BHIE register bits */
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#define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
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#define BHIE_TXVECDB_SEQNUM_SHFT 0
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#define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
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#define BHIE_TXVECSTATUS_SEQNUM_SHFT 0
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#define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
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#define BHIE_TXVECSTATUS_STATUS_SHFT 30
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#define BHIE_TXVECSTATUS_STATUS_RESET 0x00
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#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02
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#define BHIE_TXVECSTATUS_STATUS_ERROR 0x03
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#define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
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#define BHIE_RXVECDB_SEQNUM_SHFT 0
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#define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
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#define BHIE_RXVECSTATUS_SEQNUM_SHFT 0
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#define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
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#define BHIE_RXVECSTATUS_STATUS_SHFT 30
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#define BHIE_RXVECSTATUS_STATUS_RESET 0x00
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#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02
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#define BHIE_RXVECSTATUS_STATUS_ERROR 0x03
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/* MHI register bits */
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#define MHICFG_NHWER_MASK GENMASK(31, 24)
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#define MHICFG_NER_MASK GENMASK(23, 16)
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#define MHICFG_NHWCH_MASK GENMASK(15, 8)
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#define MHICFG_NCH_MASK GENMASK(7, 0)
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#define MHICTRL_MHISTATE_MASK GENMASK(15, 8)
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#define MHICTRL_RESET_MASK BIT(1)
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#define MHISTATUS_MHISTATE_MASK GENMASK(15, 8)
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#define MHISTATUS_SYSERR_MASK BIT(2)
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#define MHISTATUS_READY_MASK BIT(0)
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/* Command Ring Element macros */
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/* No operation command */
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#define MHI_TRE_CMD_NOOP_PTR 0
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#define MHI_TRE_CMD_NOOP_DWORD0 0
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#define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
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/* Channel reset command */
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#define MHI_TRE_CMD_RESET_PTR 0
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#define MHI_TRE_CMD_RESET_DWORD0 0
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#define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
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FIELD_PREP(GENMASK(23, 16), \
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MHI_CMD_RESET_CHAN))
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/* Channel stop command */
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#define MHI_TRE_CMD_STOP_PTR 0
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#define MHI_TRE_CMD_STOP_DWORD0 0
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#define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
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FIELD_PREP(GENMASK(23, 16), \
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MHI_CMD_STOP_CHAN))
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/* Channel start command */
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#define MHI_TRE_CMD_START_PTR 0
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#define MHI_TRE_CMD_START_DWORD0 0
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#define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
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FIELD_PREP(GENMASK(23, 16), \
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MHI_CMD_START_CHAN))
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#define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
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#define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
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#define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
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/* Event descriptor macros */
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#define MHI_TRE_EV_PTR(ptr) cpu_to_le64(ptr)
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#define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \
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FIELD_PREP(GENMASK(15, 0), len))
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#define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
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FIELD_PREP(GENMASK(23, 16), type))
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#define MHI_TRE_GET_EV_PTR(tre) le64_to_cpu((tre)->ptr)
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#define MHI_TRE_GET_EV_CODE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
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#define MHI_TRE_GET_EV_LEN(tre) FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))
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#define MHI_TRE_GET_EV_CHID(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
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#define MHI_TRE_GET_EV_TYPE(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))
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#define MHI_TRE_GET_EV_STATE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
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#define MHI_TRE_GET_EV_EXECENV(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
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#define MHI_TRE_GET_EV_SEQ(tre) MHI_TRE_GET_DWORD(tre, 0)
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#define MHI_TRE_GET_EV_TIME(tre) MHI_TRE_GET_EV_PTR(tre)
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#define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits(MHI_TRE_GET_EV_PTR(tre))
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#define MHI_TRE_GET_EV_VEID(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))
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#define MHI_TRE_GET_EV_LINKSPEED(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
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#define MHI_TRE_GET_EV_LINKWIDTH(tre) FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))
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/* Transfer descriptor macros */
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#define MHI_TRE_DATA_PTR(ptr) cpu_to_le64(ptr)
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#define MHI_TRE_DATA_DWORD0(len) cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))
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#define MHI_TRE_TYPE_TRANSFER 2
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#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
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MHI_TRE_TYPE_TRANSFER) | \
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FIELD_PREP(BIT(10), bei) | \
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FIELD_PREP(BIT(9), ieot) | \
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FIELD_PREP(BIT(8), ieob) | \
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FIELD_PREP(BIT(0), chain))
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/* RSC transfer descriptor macros */
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#define MHI_RSCTRE_DATA_PTR(ptr, len) cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)
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#define MHI_RSCTRE_DATA_DWORD0(cookie) cpu_to_le32(cookie)
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#define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
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MHI_PKT_TYPE_COALESCING))
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enum mhi_pkt_type {
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MHI_PKT_TYPE_INVALID = 0x0,
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MHI_PKT_TYPE_NOOP_CMD = 0x1,
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MHI_PKT_TYPE_TRANSFER = 0x2,
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MHI_PKT_TYPE_COALESCING = 0x8,
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MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10,
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MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11,
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MHI_PKT_TYPE_START_CHAN_CMD = 0x12,
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MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20,
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MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21,
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MHI_PKT_TYPE_TX_EVENT = 0x22,
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MHI_PKT_TYPE_RSC_TX_EVENT = 0x28,
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MHI_PKT_TYPE_EE_EVENT = 0x40,
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MHI_PKT_TYPE_TSYNC_EVENT = 0x48,
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MHI_PKT_TYPE_BW_REQ_EVENT = 0x50,
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MHI_PKT_TYPE_STALE_EVENT, /* internal event */
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};
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/* MHI transfer completion events */
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enum mhi_ev_ccs {
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MHI_EV_CC_INVALID = 0x0,
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MHI_EV_CC_SUCCESS = 0x1,
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MHI_EV_CC_EOT = 0x2, /* End of transfer event */
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MHI_EV_CC_OVERFLOW = 0x3,
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MHI_EV_CC_EOB = 0x4, /* End of block event */
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MHI_EV_CC_OOB = 0x5, /* Out of block event */
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MHI_EV_CC_DB_MODE = 0x6,
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MHI_EV_CC_UNDEFINED_ERR = 0x10,
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MHI_EV_CC_BAD_TRE = 0x11,
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};
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/* Channel state */
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enum mhi_ch_state {
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MHI_CH_STATE_DISABLED,
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MHI_CH_STATE_ENABLED,
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MHI_CH_STATE_RUNNING,
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MHI_CH_STATE_SUSPENDED,
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MHI_CH_STATE_STOP,
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MHI_CH_STATE_ERROR,
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};
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enum mhi_cmd_type {
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MHI_CMD_NOP = 1,
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MHI_CMD_RESET_CHAN = 16,
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MHI_CMD_STOP_CHAN = 17,
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MHI_CMD_START_CHAN = 18,
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};
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#define EV_CTX_RESERVED_MASK GENMASK(7, 0)
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#define EV_CTX_INTMODC_MASK GENMASK(15, 8)
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#define EV_CTX_INTMODT_MASK GENMASK(31, 16)
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struct mhi_event_ctxt {
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__le32 intmod;
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__le32 ertype;
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__le32 msivec;
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__le64 rbase __packed __aligned(4);
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__le64 rlen __packed __aligned(4);
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__le64 rp __packed __aligned(4);
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__le64 wp __packed __aligned(4);
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};
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#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
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#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
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#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
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#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
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struct mhi_chan_ctxt {
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__le32 chcfg;
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__le32 chtype;
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__le32 erindex;
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__le64 rbase __packed __aligned(4);
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__le64 rlen __packed __aligned(4);
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__le64 rp __packed __aligned(4);
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__le64 wp __packed __aligned(4);
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};
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struct mhi_cmd_ctxt {
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__le32 reserved0;
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__le32 reserved1;
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__le32 reserved2;
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__le64 rbase __packed __aligned(4);
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__le64 rlen __packed __aligned(4);
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__le64 rp __packed __aligned(4);
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__le64 wp __packed __aligned(4);
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};
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struct mhi_ring_element {
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__le64 ptr;
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__le32 dword[2];
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};
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static inline const char *mhi_state_str(enum mhi_state state)
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{
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switch (state) {
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case MHI_STATE_RESET:
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return "RESET";
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case MHI_STATE_READY:
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return "READY";
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case MHI_STATE_M0:
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return "M0";
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case MHI_STATE_M1:
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return "M1";
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case MHI_STATE_M2:
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return "M2";
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case MHI_STATE_M3:
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return "M3";
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case MHI_STATE_M3_FAST:
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return "M3 FAST";
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case MHI_STATE_BHI:
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return "BHI";
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case MHI_STATE_SYS_ERR:
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return "SYS ERROR";
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default:
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return "Unknown state";
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* _MHI_COMMON_H */
|