397 lines
12 KiB
C
397 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/**
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* Copyright(c) 2016-20 Intel Corporation.
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*
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* Intel Software Guard Extensions (SGX) support.
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*/
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#ifndef _ASM_X86_SGX_H
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#define _ASM_X86_SGX_H
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#include <linux/bits.h>
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#include <linux/types.h>
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/*
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* This file contains both data structures defined by SGX architecture and Linux
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* defined software data structures and functions. The two should not be mixed
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* together for better readability. The architectural definitions come first.
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*/
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/* The SGX specific CPUID function. */
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#define SGX_CPUID 0x12
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/* EPC enumeration. */
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#define SGX_CPUID_EPC 2
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/* An invalid EPC section, i.e. the end marker. */
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#define SGX_CPUID_EPC_INVALID 0x0
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/* A valid EPC section. */
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#define SGX_CPUID_EPC_SECTION 0x1
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/* The bitmask for the EPC section type. */
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#define SGX_CPUID_EPC_MASK GENMASK(3, 0)
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enum sgx_encls_function {
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ECREATE = 0x00,
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EADD = 0x01,
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EINIT = 0x02,
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EREMOVE = 0x03,
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EDGBRD = 0x04,
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EDGBWR = 0x05,
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EEXTEND = 0x06,
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ELDU = 0x08,
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EBLOCK = 0x09,
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EPA = 0x0A,
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EWB = 0x0B,
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ETRACK = 0x0C,
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EAUG = 0x0D,
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EMODPR = 0x0E,
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EMODT = 0x0F,
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};
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/**
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* SGX_ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
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*
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* ENCLS has its own (positive value) error codes and also generates
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* ENCLS specific #GP and #PF faults. And the ENCLS values get munged
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* with system error codes as everything percolates back up the stack.
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* Unfortunately (for us), we need to precisely identify each unique
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* error code, e.g. the action taken if EWB fails varies based on the
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* type of fault and on the exact SGX error code, i.e. we can't simply
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* convert all faults to -EFAULT.
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*
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* To make all three error types coexist, we set bit 30 to identify an
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* ENCLS fault. Bit 31 (technically bits N:31) is used to differentiate
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* between positive (faults and SGX error codes) and negative (system
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* error codes) values.
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*/
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#define SGX_ENCLS_FAULT_FLAG 0x40000000
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/**
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* enum sgx_return_code - The return code type for ENCLS, ENCLU and ENCLV
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* %SGX_NOT_TRACKED: Previous ETRACK's shootdown sequence has not
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* been completed yet.
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* %SGX_CHILD_PRESENT SECS has child pages present in the EPC.
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* %SGX_INVALID_EINITTOKEN: EINITTOKEN is invalid and enclave signer's
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* public key does not match IA32_SGXLEPUBKEYHASH.
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* %SGX_UNMASKED_EVENT: An unmasked event, e.g. INTR, was received
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*/
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enum sgx_return_code {
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SGX_NOT_TRACKED = 11,
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SGX_CHILD_PRESENT = 13,
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SGX_INVALID_EINITTOKEN = 16,
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SGX_UNMASKED_EVENT = 128,
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};
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/* The modulus size for 3072-bit RSA keys. */
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#define SGX_MODULUS_SIZE 384
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/**
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* enum sgx_miscselect - additional information to an SSA frame
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* %SGX_MISC_EXINFO: Report #PF or #GP to the SSA frame.
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*
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* Save State Area (SSA) is a stack inside the enclave used to store processor
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* state when an exception or interrupt occurs. This enum defines additional
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* information stored to an SSA frame.
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*/
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enum sgx_miscselect {
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SGX_MISC_EXINFO = BIT(0),
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};
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#define SGX_MISC_RESERVED_MASK GENMASK_ULL(63, 1)
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#define SGX_SSA_GPRS_SIZE 184
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#define SGX_SSA_MISC_EXINFO_SIZE 16
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/**
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* enum sgx_attributes - the attributes field in &struct sgx_secs
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* %SGX_ATTR_INIT: Enclave can be entered (is initialized).
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* %SGX_ATTR_DEBUG: Allow ENCLS(EDBGRD) and ENCLS(EDBGWR).
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* %SGX_ATTR_MODE64BIT: Tell that this a 64-bit enclave.
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* %SGX_ATTR_PROVISIONKEY: Allow to use provisioning keys for remote
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* attestation.
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* %SGX_ATTR_KSS: Allow to use key separation and sharing (KSS).
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* %SGX_ATTR_EINITTOKENKEY: Allow to use token signing key that is used to
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* sign cryptographic tokens that can be passed to
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* EINIT as an authorization to run an enclave.
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*/
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enum sgx_attribute {
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SGX_ATTR_INIT = BIT(0),
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SGX_ATTR_DEBUG = BIT(1),
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SGX_ATTR_MODE64BIT = BIT(2),
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SGX_ATTR_PROVISIONKEY = BIT(4),
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SGX_ATTR_EINITTOKENKEY = BIT(5),
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SGX_ATTR_KSS = BIT(7),
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};
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#define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) | BIT_ULL(6) | GENMASK_ULL(63, 8))
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/**
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* struct sgx_secs - SGX Enclave Control Structure (SECS)
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* @size: size of the address space
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* @base: base address of the address space
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* @ssa_frame_size: size of an SSA frame
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* @miscselect: additional information stored to an SSA frame
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* @attributes: attributes for enclave
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* @xfrm: XSave-Feature Request Mask (subset of XCR0)
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* @mrenclave: SHA256-hash of the enclave contents
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* @mrsigner: SHA256-hash of the public key used to sign the SIGSTRUCT
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* @config_id: a user-defined value that is used in key derivation
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* @isv_prod_id: a user-defined value that is used in key derivation
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* @isv_svn: a user-defined value that is used in key derivation
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* @config_svn: a user-defined value that is used in key derivation
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*
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* SGX Enclave Control Structure (SECS) is a special enclave page that is not
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* visible in the address space. In fact, this structure defines the address
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* range and other global attributes for the enclave and it is the first EPC
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* page created for any enclave. It is moved from a temporary buffer to an EPC
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* by the means of ENCLS[ECREATE] function.
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*/
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struct sgx_secs {
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u64 size;
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u64 base;
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u32 ssa_frame_size;
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u32 miscselect;
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u8 reserved1[24];
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u64 attributes;
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u64 xfrm;
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u32 mrenclave[8];
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u8 reserved2[32];
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u32 mrsigner[8];
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u8 reserved3[32];
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u32 config_id[16];
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u16 isv_prod_id;
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u16 isv_svn;
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u16 config_svn;
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u8 reserved4[3834];
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} __packed;
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/**
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* enum sgx_tcs_flags - execution flags for TCS
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* %SGX_TCS_DBGOPTIN: If enabled allows single-stepping and breakpoints
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* inside an enclave. It is cleared by EADD but can
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* be set later with EDBGWR.
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*/
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enum sgx_tcs_flags {
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SGX_TCS_DBGOPTIN = 0x01,
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};
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#define SGX_TCS_RESERVED_MASK GENMASK_ULL(63, 1)
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#define SGX_TCS_RESERVED_SIZE 4024
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/**
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* struct sgx_tcs - Thread Control Structure (TCS)
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* @state: used to mark an entered TCS
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* @flags: execution flags (cleared by EADD)
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* @ssa_offset: SSA stack offset relative to the enclave base
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* @ssa_index: the current SSA frame index (cleard by EADD)
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* @nr_ssa_frames: the number of frame in the SSA stack
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* @entry_offset: entry point offset relative to the enclave base
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* @exit_addr: address outside the enclave to exit on an exception or
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* interrupt
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* @fs_offset: offset relative to the enclave base to become FS
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* segment inside the enclave
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* @gs_offset: offset relative to the enclave base to become GS
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* segment inside the enclave
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* @fs_limit: size to become a new FS-limit (only 32-bit enclaves)
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* @gs_limit: size to become a new GS-limit (only 32-bit enclaves)
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*
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* Thread Control Structure (TCS) is an enclave page visible in its address
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* space that defines an entry point inside the enclave. A thread enters inside
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* an enclave by supplying address of TCS to ENCLU(EENTER). A TCS can be entered
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* by only one thread at a time.
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*/
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struct sgx_tcs {
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u64 state;
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u64 flags;
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u64 ssa_offset;
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u32 ssa_index;
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u32 nr_ssa_frames;
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u64 entry_offset;
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u64 exit_addr;
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u64 fs_offset;
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u64 gs_offset;
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u32 fs_limit;
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u32 gs_limit;
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u8 reserved[SGX_TCS_RESERVED_SIZE];
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} __packed;
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/**
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* struct sgx_pageinfo - an enclave page descriptor
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* @addr: address of the enclave page
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* @contents: pointer to the page contents
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* @metadata: pointer either to a SECINFO or PCMD instance
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* @secs: address of the SECS page
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*/
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struct sgx_pageinfo {
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u64 addr;
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u64 contents;
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u64 metadata;
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u64 secs;
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} __packed __aligned(32);
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/**
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* enum sgx_page_type - bits in the SECINFO flags defining the page type
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* %SGX_PAGE_TYPE_SECS: a SECS page
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* %SGX_PAGE_TYPE_TCS: a TCS page
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* %SGX_PAGE_TYPE_REG: a regular page
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* %SGX_PAGE_TYPE_VA: a VA page
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* %SGX_PAGE_TYPE_TRIM: a page in trimmed state
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*/
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enum sgx_page_type {
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SGX_PAGE_TYPE_SECS,
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SGX_PAGE_TYPE_TCS,
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SGX_PAGE_TYPE_REG,
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SGX_PAGE_TYPE_VA,
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SGX_PAGE_TYPE_TRIM,
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};
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#define SGX_NR_PAGE_TYPES 5
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#define SGX_PAGE_TYPE_MASK GENMASK(7, 0)
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/**
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* enum sgx_secinfo_flags - the flags field in &struct sgx_secinfo
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* %SGX_SECINFO_R: allow read
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* %SGX_SECINFO_W: allow write
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* %SGX_SECINFO_X: allow execution
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* %SGX_SECINFO_SECS: a SECS page
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* %SGX_SECINFO_TCS: a TCS page
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* %SGX_SECINFO_REG: a regular page
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* %SGX_SECINFO_VA: a VA page
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* %SGX_SECINFO_TRIM: a page in trimmed state
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*/
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enum sgx_secinfo_flags {
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SGX_SECINFO_R = BIT(0),
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SGX_SECINFO_W = BIT(1),
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SGX_SECINFO_X = BIT(2),
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SGX_SECINFO_SECS = (SGX_PAGE_TYPE_SECS << 8),
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SGX_SECINFO_TCS = (SGX_PAGE_TYPE_TCS << 8),
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SGX_SECINFO_REG = (SGX_PAGE_TYPE_REG << 8),
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SGX_SECINFO_VA = (SGX_PAGE_TYPE_VA << 8),
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SGX_SECINFO_TRIM = (SGX_PAGE_TYPE_TRIM << 8),
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};
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#define SGX_SECINFO_PERMISSION_MASK GENMASK_ULL(2, 0)
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#define SGX_SECINFO_PAGE_TYPE_MASK (SGX_PAGE_TYPE_MASK << 8)
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#define SGX_SECINFO_RESERVED_MASK ~(SGX_SECINFO_PERMISSION_MASK | \
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SGX_SECINFO_PAGE_TYPE_MASK)
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/**
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* struct sgx_secinfo - describes attributes of an EPC page
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* @flags: permissions and type
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*
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* Used together with ENCLS leaves that add or modify an EPC page to an
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* enclave to define page permissions and type.
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*/
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struct sgx_secinfo {
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u64 flags;
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u8 reserved[56];
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} __packed __aligned(64);
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#define SGX_PCMD_RESERVED_SIZE 40
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/**
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* struct sgx_pcmd - Paging Crypto Metadata (PCMD)
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* @enclave_id: enclave identifier
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* @mac: MAC over PCMD, page contents and isvsvn
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*
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* PCMD is stored for every swapped page to the regular memory. When ELDU loads
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* the page back it recalculates the MAC by using a isvsvn number stored in a
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* VA page. Together these two structures bring integrity and rollback
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* protection.
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*/
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struct sgx_pcmd {
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struct sgx_secinfo secinfo;
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u64 enclave_id;
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u8 reserved[SGX_PCMD_RESERVED_SIZE];
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u8 mac[16];
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} __packed __aligned(128);
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#define SGX_SIGSTRUCT_RESERVED1_SIZE 84
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#define SGX_SIGSTRUCT_RESERVED2_SIZE 20
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#define SGX_SIGSTRUCT_RESERVED3_SIZE 32
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#define SGX_SIGSTRUCT_RESERVED4_SIZE 12
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/**
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* struct sgx_sigstruct_header - defines author of the enclave
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* @header1: constant byte string
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* @vendor: must be either 0x0000 or 0x8086
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* @date: YYYYMMDD in BCD
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* @header2: constant byte string
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* @swdefined: software defined value
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*/
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struct sgx_sigstruct_header {
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u64 header1[2];
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u32 vendor;
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u32 date;
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u64 header2[2];
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u32 swdefined;
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u8 reserved1[84];
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} __packed;
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/**
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* struct sgx_sigstruct_body - defines contents of the enclave
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* @miscselect: additional information stored to an SSA frame
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* @misc_mask: required miscselect in SECS
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* @attributes: attributes for enclave
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* @xfrm: XSave-Feature Request Mask (subset of XCR0)
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* @attributes_mask: required attributes in SECS
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* @xfrm_mask: required XFRM in SECS
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* @mrenclave: SHA256-hash of the enclave contents
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* @isvprodid: a user-defined value that is used in key derivation
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* @isvsvn: a user-defined value that is used in key derivation
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*/
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struct sgx_sigstruct_body {
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u32 miscselect;
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u32 misc_mask;
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||
|
|
u8 reserved2[20];
|
||
|
|
u64 attributes;
|
||
|
|
u64 xfrm;
|
||
|
|
u64 attributes_mask;
|
||
|
|
u64 xfrm_mask;
|
||
|
|
u8 mrenclave[32];
|
||
|
|
u8 reserved3[32];
|
||
|
|
u16 isvprodid;
|
||
|
|
u16 isvsvn;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct sgx_sigstruct - an enclave signature
|
||
|
|
* @header: defines author of the enclave
|
||
|
|
* @modulus: the modulus of the public key
|
||
|
|
* @exponent: the exponent of the public key
|
||
|
|
* @signature: the signature calculated over the fields except modulus,
|
||
|
|
* @body: defines contents of the enclave
|
||
|
|
* @q1: a value used in RSA signature verification
|
||
|
|
* @q2: a value used in RSA signature verification
|
||
|
|
*
|
||
|
|
* Header and body are the parts that are actual signed. The remaining fields
|
||
|
|
* define the signature of the enclave.
|
||
|
|
*/
|
||
|
|
struct sgx_sigstruct {
|
||
|
|
struct sgx_sigstruct_header header;
|
||
|
|
u8 modulus[SGX_MODULUS_SIZE];
|
||
|
|
u32 exponent;
|
||
|
|
u8 signature[SGX_MODULUS_SIZE];
|
||
|
|
struct sgx_sigstruct_body body;
|
||
|
|
u8 reserved4[12];
|
||
|
|
u8 q1[SGX_MODULUS_SIZE];
|
||
|
|
u8 q2[SGX_MODULUS_SIZE];
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
#define SGX_LAUNCH_TOKEN_SIZE 304
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Do not put any hardware-defined SGX structure representations below this
|
||
|
|
* comment!
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef CONFIG_X86_SGX_KVM
|
||
|
|
int sgx_virt_ecreate(struct sgx_pageinfo *pageinfo, void __user *secs,
|
||
|
|
int *trapnr);
|
||
|
|
int sgx_virt_einit(void __user *sigstruct, void __user *token,
|
||
|
|
void __user *secs, u64 *lepubkeyhash, int *trapnr);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int sgx_set_attribute(unsigned long *allowed_attributes,
|
||
|
|
unsigned int attribute_fd);
|
||
|
|
|
||
|
|
#endif /* _ASM_X86_SGX_H */
|