475 lines
12 KiB
C
475 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* This file contains common routines for dealing with free of page tables
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* Along with common page table handling code
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*
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* Derived from arch/powerpc/mm/tlb_64.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*/
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#include <linux/kernel.h>
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#include <linux/gfp.h>
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#include <linux/mm.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/hugetlb.h>
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#include <asm/pte-walk.h>
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#ifdef CONFIG_PPC64
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#define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD)
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#else
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#define PGD_ALIGN PAGE_SIZE
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#endif
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pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN);
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static inline int is_exec_fault(void)
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{
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return current->thread.regs && TRAP(current->thread.regs) == 0x400;
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}
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/* We only try to do i/d cache coherency on stuff that looks like
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* reasonably "normal" PTEs. We currently require a PTE to be present
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* and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
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* on userspace PTEs
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*/
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static inline int pte_looks_normal(pte_t pte)
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{
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if (pte_present(pte) && !pte_special(pte)) {
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if (pte_ci(pte))
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return 0;
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if (pte_user(pte))
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return 1;
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}
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return 0;
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}
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static struct page *maybe_pte_to_page(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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if (unlikely(!pfn_valid(pfn)))
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return NULL;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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return NULL;
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return page;
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}
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#ifdef CONFIG_PPC_BOOK3S
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/* Server-style MMU handles coherency when hashing if HW exec permission
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* is supposed per page (currently 64-bit only). If not, then, we always
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* flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
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* support falls into the same category.
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*/
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static pte_t set_pte_filter_hash(pte_t pte)
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{
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pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
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if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
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cpu_has_feature(CPU_FTR_NOEXECUTE))) {
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struct page *pg = maybe_pte_to_page(pte);
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if (!pg)
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return pte;
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if (!test_bit(PG_dcache_clean, &pg->flags)) {
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flush_dcache_icache_page(pg);
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set_bit(PG_dcache_clean, &pg->flags);
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}
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}
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return pte;
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}
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#else /* CONFIG_PPC_BOOK3S */
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static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
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#endif /* CONFIG_PPC_BOOK3S */
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/* Embedded type MMU with HW exec support. This is a bit more complicated
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* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
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* instead we "filter out" the exec permission for non clean pages.
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*/
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static inline pte_t set_pte_filter(pte_t pte)
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{
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struct page *pg;
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if (radix_enabled())
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return pte;
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
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return set_pte_filter_hash(pte);
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/* No exec permission in the first place, move on */
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if (!pte_exec(pte) || !pte_looks_normal(pte))
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return pte;
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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return pte;
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/* If the page clean, we move on */
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if (test_bit(PG_dcache_clean, &pg->flags))
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return pte;
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/* If it's an exec fault, we flush the cache and make it clean */
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if (is_exec_fault()) {
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flush_dcache_icache_page(pg);
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set_bit(PG_dcache_clean, &pg->flags);
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return pte;
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}
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/* Else, we filter out _PAGE_EXEC */
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return pte_exprotect(pte);
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}
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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struct page *pg;
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
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return pte;
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
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return pte;
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/* So here, we only care about exec faults, as we use them
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* to recover lost _PAGE_EXEC and perform I$/D$ coherency
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* if necessary. Also if _PAGE_EXEC is already set, same deal,
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* we just bail out
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*/
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if (dirty || pte_exec(pte) || !is_exec_fault())
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return pte;
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#ifdef CONFIG_DEBUG_VM
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/* So this is an exec fault, _PAGE_EXEC is not set. If it was
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* an error we would have bailed out earlier in do_page_fault()
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* but let's make sure of it
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*/
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if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
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return pte;
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#endif /* CONFIG_DEBUG_VM */
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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goto bail;
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/* If the page is already clean, we move on */
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if (test_bit(PG_dcache_clean, &pg->flags))
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goto bail;
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/* Clean the page and set PG_dcache_clean */
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flush_dcache_icache_page(pg);
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set_bit(PG_dcache_clean, &pg->flags);
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bail:
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return pte_mkexec(pte);
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}
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/*
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* set_pte stores a linux PTE into the linux page table.
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*/
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void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte)
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{
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
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/* Note: mm->context.id might not yet have been assigned as
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* this context might not have been activated yet when this
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* is called.
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*/
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pte = set_pte_filter(pte);
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/* Perform the setting of the PTE */
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__set_pte_at(mm, addr, ptep, pte, 0);
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}
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void unmap_kernel_page(unsigned long va)
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{
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pmd_t *pmdp = pmd_off_k(va);
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pte_t *ptep = pte_offset_kernel(pmdp, va);
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pte_clear(&init_mm, va, ptep);
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flush_tlb_kernel_range(va, va + PAGE_SIZE);
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}
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/*
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* This is called when relaxing access to a PTE. It's also called in the page
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* fault path when we don't hit any of the major fault cases, ie, a minor
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* update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
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* handled those two for us, we additionally deal with missing execute
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* permission here on some processors
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*/
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int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty)
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{
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int changed;
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entry = set_access_flags_filter(entry, vma, dirty);
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changed = !pte_same(*(ptep), entry);
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if (changed) {
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assert_pte_locked(vma->vm_mm, address);
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__ptep_set_access_flags(vma, ptep, entry,
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address, mmu_virtual_psize);
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}
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return changed;
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}
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#ifdef CONFIG_HUGETLB_PAGE
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int huge_ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t pte, int dirty)
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{
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#ifdef HUGETLB_NEED_PRELOAD
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/*
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* The "return 1" forces a call of update_mmu_cache, which will write a
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* TLB entry. Without this, platforms that don't do a write of the TLB
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* entry in the TLB miss handler asm will fault ad infinitum.
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*/
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ptep_set_access_flags(vma, addr, ptep, pte, dirty);
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return 1;
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#else
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int changed, psize;
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pte = set_access_flags_filter(pte, vma, dirty);
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changed = !pte_same(*(ptep), pte);
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if (changed) {
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#ifdef CONFIG_PPC_BOOK3S_64
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struct hstate *h = hstate_vma(vma);
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psize = hstate_get_psize(h);
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#ifdef CONFIG_DEBUG_VM
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assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
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#endif
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#else
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/*
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* Not used on non book3s64 platforms.
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* 8xx compares it with mmu_virtual_psize to
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* know if it is a huge page or not.
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*/
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psize = MMU_PAGE_COUNT;
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#endif
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__ptep_set_access_flags(vma, ptep, pte, addr, psize);
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}
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return changed;
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#endif
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}
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#if defined(CONFIG_PPC_8xx)
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void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
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{
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pmd_t *pmd = pmd_off(mm, addr);
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pte_basic_t val;
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pte_basic_t *entry = (pte_basic_t *)ptep;
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int num, i;
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
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pte = set_pte_filter(pte);
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val = pte_val(pte);
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num = number_of_cells_per_pte(pmd, val, 1);
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for (i = 0; i < num; i++, entry++, val += SZ_4K)
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*entry = val;
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}
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#endif
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#endif /* CONFIG_HUGETLB_PAGE */
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#ifdef CONFIG_DEBUG_VM
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void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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pgd_t *pgd;
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p4d_t *p4d;
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pud_t *pud;
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pmd_t *pmd;
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if (mm == &init_mm)
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return;
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pgd = mm->pgd + pgd_index(addr);
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BUG_ON(pgd_none(*pgd));
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p4d = p4d_offset(pgd, addr);
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BUG_ON(p4d_none(*p4d));
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pud = pud_offset(p4d, addr);
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BUG_ON(pud_none(*pud));
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pmd = pmd_offset(pud, addr);
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/*
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* khugepaged to collapse normal pages to hugepage, first set
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* pmd to none to force page fault/gup to take mmap_lock. After
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* pmd is set to none, we do a pte_clear which does this assertion
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* so if we find pmd none, return.
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*/
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if (pmd_none(*pmd))
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return;
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BUG_ON(!pmd_present(*pmd));
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assert_spin_locked(pte_lockptr(mm, pmd));
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}
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#endif /* CONFIG_DEBUG_VM */
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unsigned long vmalloc_to_phys(void *va)
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{
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unsigned long pfn = vmalloc_to_pfn(va);
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BUG_ON(!pfn);
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return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
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}
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EXPORT_SYMBOL_GPL(vmalloc_to_phys);
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/*
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* We have 4 cases for pgds and pmds:
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* (1) invalid (all zeroes)
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* (2) pointer to next table, as normal; bottom 6 bits == 0
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* (3) leaf pte for huge page _PAGE_PTE set
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* (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
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*
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* So long as we atomically load page table pointers we are safe against teardown,
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* we can follow the address down to the the page and take a ref on it.
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* This function need to be called with interrupts disabled. We use this variant
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* when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
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*/
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pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
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bool *is_thp, unsigned *hpage_shift)
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{
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pgd_t *pgdp;
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p4d_t p4d, *p4dp;
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pud_t pud, *pudp;
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pmd_t pmd, *pmdp;
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pte_t *ret_pte;
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hugepd_t *hpdp = NULL;
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unsigned pdshift;
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if (hpage_shift)
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*hpage_shift = 0;
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if (is_thp)
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*is_thp = false;
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/*
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* Always operate on the local stack value. This make sure the
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* value don't get updated by a parallel THP split/collapse,
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* page fault or a page unmap. The return pte_t * is still not
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* stable. So should be checked there for above conditions.
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* Top level is an exception because it is folded into p4d.
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*/
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pgdp = pgdir + pgd_index(ea);
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p4dp = p4d_offset(pgdp, ea);
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p4d = READ_ONCE(*p4dp);
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pdshift = P4D_SHIFT;
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if (p4d_none(p4d))
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return NULL;
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if (p4d_is_leaf(p4d)) {
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ret_pte = (pte_t *)p4dp;
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goto out;
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}
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if (is_hugepd(__hugepd(p4d_val(p4d)))) {
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hpdp = (hugepd_t *)&p4d;
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goto out_huge;
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}
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/*
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* Even if we end up with an unmap, the pgtable will not
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* be freed, because we do an rcu free and here we are
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* irq disabled
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*/
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pdshift = PUD_SHIFT;
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pudp = pud_offset(&p4d, ea);
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pud = READ_ONCE(*pudp);
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if (pud_none(pud))
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return NULL;
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if (pud_is_leaf(pud)) {
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ret_pte = (pte_t *)pudp;
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goto out;
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}
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if (is_hugepd(__hugepd(pud_val(pud)))) {
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hpdp = (hugepd_t *)&pud;
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goto out_huge;
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|
}
|
||
|
|
||
|
pdshift = PMD_SHIFT;
|
||
|
pmdp = pmd_offset(&pud, ea);
|
||
|
pmd = READ_ONCE(*pmdp);
|
||
|
|
||
|
/*
|
||
|
* A hugepage collapse is captured by this condition, see
|
||
|
* pmdp_collapse_flush.
|
||
|
*/
|
||
|
if (pmd_none(pmd))
|
||
|
return NULL;
|
||
|
|
||
|
#ifdef CONFIG_PPC_BOOK3S_64
|
||
|
/*
|
||
|
* A hugepage split is captured by this condition, see
|
||
|
* pmdp_invalidate.
|
||
|
*
|
||
|
* Huge page modification can be caught here too.
|
||
|
*/
|
||
|
if (pmd_is_serializing(pmd))
|
||
|
return NULL;
|
||
|
#endif
|
||
|
|
||
|
if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
|
||
|
if (is_thp)
|
||
|
*is_thp = true;
|
||
|
ret_pte = (pte_t *)pmdp;
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
if (pmd_is_leaf(pmd)) {
|
||
|
ret_pte = (pte_t *)pmdp;
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
if (is_hugepd(__hugepd(pmd_val(pmd)))) {
|
||
|
hpdp = (hugepd_t *)&pmd;
|
||
|
goto out_huge;
|
||
|
}
|
||
|
|
||
|
return pte_offset_kernel(&pmd, ea);
|
||
|
|
||
|
out_huge:
|
||
|
if (!hpdp)
|
||
|
return NULL;
|
||
|
|
||
|
ret_pte = hugepte_offset(*hpdp, ea, pdshift);
|
||
|
pdshift = hugepd_shift(*hpdp);
|
||
|
out:
|
||
|
if (hpage_shift)
|
||
|
*hpage_shift = pdshift;
|
||
|
return ret_pte;
|
||
|
}
|
||
|
EXPORT_SYMBOL_GPL(__find_linux_pte);
|