706 lines
18 KiB
C
706 lines
18 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/cpu.h>
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#include <linux/kvm_host.h>
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#include <linux/preempt.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/memblock.h>
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#include <linux/sizes.h>
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#include <linux/cma.h>
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#include <linux/bitops.h>
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#include <asm/cputable.h>
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#include <asm/interrupt.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/archrandom.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/dbell.h>
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#include <asm/cputhreads.h>
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#include <asm/io.h>
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#include <asm/opal.h>
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#include <asm/smp.h>
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#define KVM_CMA_CHUNK_ORDER 18
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#include "book3s_xics.h"
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#include "book3s_xive.h"
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/*
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* Hash page table alignment on newer cpus(CPU_FTR_ARCH_206)
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* should be power of 2.
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*/
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#define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */
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/*
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* By default we reserve 5% of memory for hash pagetable allocation.
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*/
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static unsigned long kvm_cma_resv_ratio = 5;
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static struct cma *kvm_cma;
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static int __init early_parse_kvm_cma_resv(char *p)
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{
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pr_debug("%s(%s)\n", __func__, p);
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if (!p)
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return -EINVAL;
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return kstrtoul(p, 0, &kvm_cma_resv_ratio);
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}
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early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv);
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struct page *kvm_alloc_hpt_cma(unsigned long nr_pages)
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{
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VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
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return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES),
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false);
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}
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EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma);
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void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages)
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{
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cma_release(kvm_cma, page, nr_pages);
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}
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EXPORT_SYMBOL_GPL(kvm_free_hpt_cma);
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/**
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* kvm_cma_reserve() - reserve area for kvm hash pagetable
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*
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* This function reserves memory from early allocator. It should be
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* called by arch specific code once the memblock allocator
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* has been activated and all other subsystems have already allocated/reserved
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* memory.
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*/
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void __init kvm_cma_reserve(void)
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{
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unsigned long align_size;
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phys_addr_t selected_size;
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/*
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* We need CMA reservation only when we are in HV mode
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*/
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return;
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selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100);
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if (selected_size) {
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pr_info("%s: reserving %ld MiB for global area\n", __func__,
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(unsigned long)selected_size / SZ_1M);
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align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
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cma_declare_contiguous(0, selected_size, 0, align_size,
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KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma",
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&kvm_cma);
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}
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}
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/*
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* Real-mode H_CONFER implementation.
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* We check if we are the only vcpu out of this virtual core
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* still running in the guest and not ceded. If so, we pop up
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* to the virtual-mode implementation; if not, just return to
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* the guest.
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*/
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long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target,
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unsigned int yield_count)
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{
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struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
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int ptid = local_paca->kvm_hstate.ptid;
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int threads_running;
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int threads_ceded;
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int threads_conferring;
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u64 stop = get_tb() + 10 * tb_ticks_per_usec;
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int rv = H_SUCCESS; /* => don't yield */
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set_bit(ptid, &vc->conferring_threads);
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while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) {
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threads_running = VCORE_ENTRY_MAP(vc);
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threads_ceded = vc->napping_threads;
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threads_conferring = vc->conferring_threads;
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if ((threads_ceded | threads_conferring) == threads_running) {
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rv = H_TOO_HARD; /* => do yield */
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break;
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}
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}
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clear_bit(ptid, &vc->conferring_threads);
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return rv;
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}
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/*
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* When running HV mode KVM we need to block certain operations while KVM VMs
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* exist in the system. We use a counter of VMs to track this.
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*
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* One of the operations we need to block is onlining of secondaries, so we
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* protect hv_vm_count with cpus_read_lock/unlock().
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*/
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static atomic_t hv_vm_count;
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void kvm_hv_vm_activated(void)
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{
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cpus_read_lock();
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atomic_inc(&hv_vm_count);
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cpus_read_unlock();
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}
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EXPORT_SYMBOL_GPL(kvm_hv_vm_activated);
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void kvm_hv_vm_deactivated(void)
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{
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cpus_read_lock();
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atomic_dec(&hv_vm_count);
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cpus_read_unlock();
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}
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EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated);
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bool kvm_hv_mode_active(void)
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{
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return atomic_read(&hv_vm_count) != 0;
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}
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extern int hcall_real_table[], hcall_real_table_end[];
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int kvmppc_hcall_impl_hv_realmode(unsigned long cmd)
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{
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cmd /= 4;
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if (cmd < hcall_real_table_end - hcall_real_table &&
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hcall_real_table[cmd])
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return 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode);
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int kvmppc_hwrng_present(void)
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{
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return powernv_hwrng_present();
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}
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EXPORT_SYMBOL_GPL(kvmppc_hwrng_present);
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long kvmppc_rm_h_random(struct kvm_vcpu *vcpu)
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{
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if (powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]))
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return H_SUCCESS;
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return H_HARDWARE;
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}
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/*
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* Send an interrupt or message to another CPU.
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* The caller needs to include any barrier needed to order writes
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* to memory vs. the IPI/message.
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*/
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void kvmhv_rm_send_ipi(int cpu)
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{
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void __iomem *xics_phys;
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unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
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/* On POWER9 we can use msgsnd for any destination cpu. */
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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msg |= get_hard_smp_processor_id(cpu);
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__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
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return;
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}
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/* On POWER8 for IPIs to threads in the same core, use msgsnd. */
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if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
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cpu_first_thread_sibling(cpu) ==
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cpu_first_thread_sibling(raw_smp_processor_id())) {
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msg |= cpu_thread_in_core(cpu);
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__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
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return;
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}
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/* We should never reach this */
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if (WARN_ON_ONCE(xics_on_xive()))
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return;
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/* Else poke the target with an IPI */
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xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys;
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if (xics_phys)
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__raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
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else
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opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
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}
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/*
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* The following functions are called from the assembly code
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* in book3s_hv_rmhandlers.S.
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*/
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static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active)
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{
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int cpu = vc->pcpu;
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/* Order setting of exit map vs. msgsnd/IPI */
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smp_mb();
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for (; active; active >>= 1, ++cpu)
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if (active & 1)
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kvmhv_rm_send_ipi(cpu);
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}
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void kvmhv_commence_exit(int trap)
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{
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struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
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int ptid = local_paca->kvm_hstate.ptid;
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struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode;
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int me, ee, i;
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/* Set our bit in the threads-exiting-guest map in the 0xff00
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bits of vcore->entry_exit_map */
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me = 0x100 << ptid;
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do {
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ee = vc->entry_exit_map;
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} while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee);
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/* Are we the first here? */
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if ((ee >> 8) != 0)
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return;
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/*
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* Trigger the other threads in this vcore to exit the guest.
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* If this is a hypervisor decrementer interrupt then they
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* will be already on their way out of the guest.
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*/
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if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER)
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kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid));
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/*
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* If we are doing dynamic micro-threading, interrupt the other
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* subcores to pull them out of their guests too.
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*/
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if (!sip)
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return;
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for (i = 0; i < MAX_SUBCORES; ++i) {
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vc = sip->vc[i];
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if (!vc)
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break;
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do {
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ee = vc->entry_exit_map;
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/* Already asked to exit? */
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if ((ee >> 8) != 0)
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break;
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} while (cmpxchg(&vc->entry_exit_map, ee,
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ee | VCORE_EXIT_REQ) != ee);
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if ((ee >> 8) == 0)
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kvmhv_interrupt_vcore(vc, ee);
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}
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}
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struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv;
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EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv);
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#ifdef CONFIG_KVM_XICS
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static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap,
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u32 xisr)
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{
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int i;
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/*
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* We access the mapped array here without a lock. That
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* is safe because we never reduce the number of entries
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* in the array and we never change the v_hwirq field of
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* an entry once it is set.
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*
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* We have also carefully ordered the stores in the writer
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* and the loads here in the reader, so that if we find a matching
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* hwirq here, the associated GSI and irq_desc fields are valid.
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*/
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for (i = 0; i < pimap->n_mapped; i++) {
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if (xisr == pimap->mapped[i].r_hwirq) {
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/*
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* Order subsequent reads in the caller to serialize
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* with the writer.
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*/
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smp_rmb();
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return &pimap->mapped[i];
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}
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}
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return NULL;
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}
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/*
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* If we have an interrupt that's not an IPI, check if we have a
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* passthrough adapter and if so, check if this external interrupt
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* is for the adapter.
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* We will attempt to deliver the IRQ directly to the target VCPU's
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* ICP, the virtual ICP (based on affinity - the xive value in ICS).
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*
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* If the delivery fails or if this is not for a passthrough adapter,
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* return to the host to handle this interrupt. We earlier
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* saved a copy of the XIRR in the PACA, it will be picked up by
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* the host ICP driver.
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*/
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static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
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{
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struct kvmppc_passthru_irqmap *pimap;
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struct kvmppc_irq_map *irq_map;
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struct kvm_vcpu *vcpu;
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vcpu = local_paca->kvm_hstate.kvm_vcpu;
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if (!vcpu)
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return 1;
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pimap = kvmppc_get_passthru_irqmap(vcpu->kvm);
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if (!pimap)
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return 1;
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irq_map = get_irqmap(pimap, xisr);
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if (!irq_map)
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return 1;
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/* We're handling this interrupt, generic code doesn't need to */
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local_paca->kvm_hstate.saved_xirr = 0;
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return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again);
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}
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#else
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static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
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{
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return 1;
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}
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#endif
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/*
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* Determine what sort of external interrupt is pending (if any).
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* Returns:
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* 0 if no interrupt is pending
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* 1 if an interrupt is pending that needs to be handled by the host
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* 2 Passthrough that needs completion in the host
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* -1 if there was a guest wakeup IPI (which has now been cleared)
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* -2 if there is PCI passthrough external interrupt that was handled
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*/
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static long kvmppc_read_one_intr(bool *again);
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long kvmppc_read_intr(void)
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{
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long ret = 0;
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long rc;
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bool again;
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if (xive_enabled())
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return 1;
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do {
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again = false;
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rc = kvmppc_read_one_intr(&again);
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if (rc && (ret == 0 || rc > ret))
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ret = rc;
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} while (again);
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return ret;
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}
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static long kvmppc_read_one_intr(bool *again)
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{
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void __iomem *xics_phys;
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u32 h_xirr;
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__be32 xirr;
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u32 xisr;
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u8 host_ipi;
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int64_t rc;
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if (xive_enabled())
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return 1;
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/* see if a host IPI is pending */
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host_ipi = local_paca->kvm_hstate.host_ipi;
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if (host_ipi)
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return 1;
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/* Now read the interrupt from the ICP */
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xics_phys = local_paca->kvm_hstate.xics_phys;
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rc = 0;
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if (!xics_phys)
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rc = opal_int_get_xirr(&xirr, false);
|
||
|
else
|
||
|
xirr = __raw_rm_readl(xics_phys + XICS_XIRR);
|
||
|
if (rc < 0)
|
||
|
return 1;
|
||
|
|
||
|
/*
|
||
|
* Save XIRR for later. Since we get control in reverse endian
|
||
|
* on LE systems, save it byte reversed and fetch it back in
|
||
|
* host endian. Note that xirr is the value read from the
|
||
|
* XIRR register, while h_xirr is the host endian version.
|
||
|
*/
|
||
|
h_xirr = be32_to_cpu(xirr);
|
||
|
local_paca->kvm_hstate.saved_xirr = h_xirr;
|
||
|
xisr = h_xirr & 0xffffff;
|
||
|
/*
|
||
|
* Ensure that the store/load complete to guarantee all side
|
||
|
* effects of loading from XIRR has completed
|
||
|
*/
|
||
|
smp_mb();
|
||
|
|
||
|
/* if nothing pending in the ICP */
|
||
|
if (!xisr)
|
||
|
return 0;
|
||
|
|
||
|
/* We found something in the ICP...
|
||
|
*
|
||
|
* If it is an IPI, clear the MFRR and EOI it.
|
||
|
*/
|
||
|
if (xisr == XICS_IPI) {
|
||
|
rc = 0;
|
||
|
if (xics_phys) {
|
||
|
__raw_rm_writeb(0xff, xics_phys + XICS_MFRR);
|
||
|
__raw_rm_writel(xirr, xics_phys + XICS_XIRR);
|
||
|
} else {
|
||
|
opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
|
||
|
rc = opal_int_eoi(h_xirr);
|
||
|
}
|
||
|
/* If rc > 0, there is another interrupt pending */
|
||
|
*again = rc > 0;
|
||
|
|
||
|
/*
|
||
|
* Need to ensure side effects of above stores
|
||
|
* complete before proceeding.
|
||
|
*/
|
||
|
smp_mb();
|
||
|
|
||
|
/*
|
||
|
* We need to re-check host IPI now in case it got set in the
|
||
|
* meantime. If it's clear, we bounce the interrupt to the
|
||
|
* guest
|
||
|
*/
|
||
|
host_ipi = local_paca->kvm_hstate.host_ipi;
|
||
|
if (unlikely(host_ipi != 0)) {
|
||
|
/* We raced with the host,
|
||
|
* we need to resend that IPI, bummer
|
||
|
*/
|
||
|
if (xics_phys)
|
||
|
__raw_rm_writeb(IPI_PRIORITY,
|
||
|
xics_phys + XICS_MFRR);
|
||
|
else
|
||
|
opal_int_set_mfrr(hard_smp_processor_id(),
|
||
|
IPI_PRIORITY);
|
||
|
/* Let side effects complete */
|
||
|
smp_mb();
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
/* OK, it's an IPI for us */
|
||
|
local_paca->kvm_hstate.saved_xirr = 0;
|
||
|
return -1;
|
||
|
}
|
||
|
|
||
|
return kvmppc_check_passthru(xisr, xirr, again);
|
||
|
}
|
||
|
|
||
|
#ifdef CONFIG_KVM_XICS
|
||
|
unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_xirr(vcpu);
|
||
|
else
|
||
|
return xics_rm_h_xirr(vcpu);
|
||
|
}
|
||
|
|
||
|
unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
vcpu->arch.regs.gpr[5] = get_tb();
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_xirr(vcpu);
|
||
|
else
|
||
|
return xics_rm_h_xirr(vcpu);
|
||
|
}
|
||
|
|
||
|
unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_ipoll(vcpu, server);
|
||
|
else
|
||
|
return H_TOO_HARD;
|
||
|
}
|
||
|
|
||
|
int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
||
|
unsigned long mfrr)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_ipi(vcpu, server, mfrr);
|
||
|
else
|
||
|
return xics_rm_h_ipi(vcpu, server, mfrr);
|
||
|
}
|
||
|
|
||
|
int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_cppr(vcpu, cppr);
|
||
|
else
|
||
|
return xics_rm_h_cppr(vcpu, cppr);
|
||
|
}
|
||
|
|
||
|
int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
|
||
|
{
|
||
|
if (!kvmppc_xics_enabled(vcpu))
|
||
|
return H_TOO_HARD;
|
||
|
if (xics_on_xive())
|
||
|
return xive_rm_h_eoi(vcpu, xirr);
|
||
|
else
|
||
|
return xics_rm_h_eoi(vcpu, xirr);
|
||
|
}
|
||
|
#endif /* CONFIG_KVM_XICS */
|
||
|
|
||
|
void kvmppc_bad_interrupt(struct pt_regs *regs)
|
||
|
{
|
||
|
/*
|
||
|
* 100 could happen at any time, 200 can happen due to invalid real
|
||
|
* address access for example (or any time due to a hardware problem).
|
||
|
*/
|
||
|
if (TRAP(regs) == 0x100) {
|
||
|
get_paca()->in_nmi++;
|
||
|
system_reset_exception(regs);
|
||
|
get_paca()->in_nmi--;
|
||
|
} else if (TRAP(regs) == 0x200) {
|
||
|
machine_check_exception(regs);
|
||
|
} else {
|
||
|
die("Bad interrupt in KVM entry/exit code", regs, SIGABRT);
|
||
|
}
|
||
|
panic("Bad KVM trap");
|
||
|
}
|
||
|
|
||
|
static void kvmppc_end_cede(struct kvm_vcpu *vcpu)
|
||
|
{
|
||
|
vcpu->arch.ceded = 0;
|
||
|
if (vcpu->arch.timer_running) {
|
||
|
hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
|
||
|
vcpu->arch.timer_running = 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr)
|
||
|
{
|
||
|
/* Guest must always run with ME enabled, HV disabled. */
|
||
|
msr = (msr | MSR_ME) & ~MSR_HV;
|
||
|
|
||
|
/*
|
||
|
* Check for illegal transactional state bit combination
|
||
|
* and if we find it, force the TS field to a safe state.
|
||
|
*/
|
||
|
if ((msr & MSR_TS_MASK) == MSR_TS_MASK)
|
||
|
msr &= ~MSR_TS_MASK;
|
||
|
vcpu->arch.shregs.msr = msr;
|
||
|
kvmppc_end_cede(vcpu);
|
||
|
}
|
||
|
EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv);
|
||
|
|
||
|
static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags)
|
||
|
{
|
||
|
unsigned long msr, pc, new_msr, new_pc;
|
||
|
|
||
|
msr = kvmppc_get_msr(vcpu);
|
||
|
pc = kvmppc_get_pc(vcpu);
|
||
|
new_msr = vcpu->arch.intr_msr;
|
||
|
new_pc = vec;
|
||
|
|
||
|
/* If transactional, change to suspend mode on IRQ delivery */
|
||
|
if (MSR_TM_TRANSACTIONAL(msr))
|
||
|
new_msr |= MSR_TS_S;
|
||
|
else
|
||
|
new_msr |= msr & MSR_TS_MASK;
|
||
|
|
||
|
/*
|
||
|
* Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and
|
||
|
* applicable. AIL=2 is not supported.
|
||
|
*
|
||
|
* AIL does not apply to SRESET, MCE, or HMI (which is never
|
||
|
* delivered to the guest), and does not apply if IR=0 or DR=0.
|
||
|
*/
|
||
|
if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET &&
|
||
|
vec != BOOK3S_INTERRUPT_MACHINE_CHECK &&
|
||
|
(vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 &&
|
||
|
(msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) {
|
||
|
new_msr |= MSR_IR | MSR_DR;
|
||
|
new_pc += 0xC000000000004000ULL;
|
||
|
}
|
||
|
|
||
|
kvmppc_set_srr0(vcpu, pc);
|
||
|
kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags);
|
||
|
kvmppc_set_pc(vcpu, new_pc);
|
||
|
vcpu->arch.shregs.msr = new_msr;
|
||
|
}
|
||
|
|
||
|
void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags)
|
||
|
{
|
||
|
inject_interrupt(vcpu, vec, srr1_flags);
|
||
|
kvmppc_end_cede(vcpu);
|
||
|
}
|
||
|
EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv);
|
||
|
|
||
|
/*
|
||
|
* Is there a PRIV_DOORBELL pending for the guest (on POWER9)?
|
||
|
* Can we inject a Decrementer or a External interrupt?
|
||
|
*/
|
||
|
void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu)
|
||
|
{
|
||
|
int ext;
|
||
|
unsigned long lpcr;
|
||
|
|
||
|
WARN_ON_ONCE(cpu_has_feature(CPU_FTR_ARCH_300));
|
||
|
|
||
|
/* Insert EXTERNAL bit into LPCR at the MER bit position */
|
||
|
ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1;
|
||
|
lpcr = mfspr(SPRN_LPCR);
|
||
|
lpcr |= ext << LPCR_MER_SH;
|
||
|
mtspr(SPRN_LPCR, lpcr);
|
||
|
isync();
|
||
|
|
||
|
if (vcpu->arch.shregs.msr & MSR_EE) {
|
||
|
if (ext) {
|
||
|
inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0);
|
||
|
} else {
|
||
|
long int dec = mfspr(SPRN_DEC);
|
||
|
if (!(lpcr & LPCR_LD))
|
||
|
dec = (int) dec;
|
||
|
if (dec < 0)
|
||
|
inject_interrupt(vcpu,
|
||
|
BOOK3S_INTERRUPT_DECREMENTER, 0);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (vcpu->arch.doorbell_request) {
|
||
|
mtspr(SPRN_DPDES, 1);
|
||
|
vcpu->arch.vcore->dpdes = 1;
|
||
|
smp_wmb();
|
||
|
vcpu->arch.doorbell_request = 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static void flush_guest_tlb(struct kvm *kvm)
|
||
|
{
|
||
|
unsigned long rb, set;
|
||
|
|
||
|
rb = PPC_BIT(52); /* IS = 2 */
|
||
|
for (set = 0; set < kvm->arch.tlb_sets; ++set) {
|
||
|
/* R=0 PRS=0 RIC=0 */
|
||
|
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
|
||
|
: : "r" (rb), "i" (0), "i" (0), "i" (0),
|
||
|
"r" (0) : "memory");
|
||
|
rb += PPC_BIT(51); /* increment set number */
|
||
|
}
|
||
|
asm volatile("ptesync": : :"memory");
|
||
|
}
|
||
|
|
||
|
void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu)
|
||
|
{
|
||
|
if (cpumask_test_cpu(pcpu, &kvm->arch.need_tlb_flush)) {
|
||
|
flush_guest_tlb(kvm);
|
||
|
|
||
|
/* Clear the bit after the TLB flush */
|
||
|
cpumask_clear_cpu(pcpu, &kvm->arch.need_tlb_flush);
|
||
|
}
|
||
|
}
|
||
|
EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush);
|