325 lines
9.5 KiB
C
325 lines
9.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
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#define _ASM_POWERPC_MMU_BOOK3E_H_
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/*
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* Freescale Book-E/Book-3e (ISA 2.06+) MMU support
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*/
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/* Book-3e defined page sizes */
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#define BOOK3E_PAGESZ_1K 0
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#define BOOK3E_PAGESZ_2K 1
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#define BOOK3E_PAGESZ_4K 2
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#define BOOK3E_PAGESZ_8K 3
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#define BOOK3E_PAGESZ_16K 4
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#define BOOK3E_PAGESZ_32K 5
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#define BOOK3E_PAGESZ_64K 6
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#define BOOK3E_PAGESZ_128K 7
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#define BOOK3E_PAGESZ_256K 8
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#define BOOK3E_PAGESZ_512K 9
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#define BOOK3E_PAGESZ_1M 10
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#define BOOK3E_PAGESZ_2M 11
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#define BOOK3E_PAGESZ_4M 12
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#define BOOK3E_PAGESZ_8M 13
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#define BOOK3E_PAGESZ_16M 14
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#define BOOK3E_PAGESZ_32M 15
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#define BOOK3E_PAGESZ_64M 16
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#define BOOK3E_PAGESZ_128M 17
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#define BOOK3E_PAGESZ_256M 18
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#define BOOK3E_PAGESZ_512M 19
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#define BOOK3E_PAGESZ_1GB 20
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#define BOOK3E_PAGESZ_2GB 21
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#define BOOK3E_PAGESZ_4GB 22
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#define BOOK3E_PAGESZ_8GB 23
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#define BOOK3E_PAGESZ_16GB 24
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#define BOOK3E_PAGESZ_32GB 25
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#define BOOK3E_PAGESZ_64GB 26
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#define BOOK3E_PAGESZ_128GB 27
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#define BOOK3E_PAGESZ_256GB 28
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#define BOOK3E_PAGESZ_512GB 29
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#define BOOK3E_PAGESZ_1TB 30
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#define BOOK3E_PAGESZ_2TB 31
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/* MAS registers bit definitions */
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#define MAS0_TLBSEL_MASK 0x30000000
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#define MAS0_TLBSEL_SHIFT 28
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#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK)
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#define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> \
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MAS0_TLBSEL_SHIFT)
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#define MAS0_ESEL_MASK 0x0FFF0000
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#define MAS0_ESEL_SHIFT 16
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#define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
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#define MAS0_NV(x) ((x) & 0x00000FFF)
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#define MAS0_HES 0x00004000
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#define MAS0_WQ_ALLWAYS 0x00000000
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#define MAS0_WQ_COND 0x00001000
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#define MAS0_WQ_CLR_RSRV 0x00002000
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
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#define MAS1_IND 0x00002000
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#define MAS1_TS 0x00001000
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#define MAS1_TSIZE_MASK 0x00000f80
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#define MAS1_TSIZE_SHIFT 7
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#define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
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#define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT)
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#define MAS2_EPN (~0xFFFUL)
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS2_WIMGE_MASK 0x0000001f
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#define MAS2_EPN_MASK(size) (~0 << (size + 10))
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#define MAS3_RPN 0xFFFFF000
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS3_BAP_MASK 0x0000003f
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#define MAS3_SPSIZE 0x0000003e
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#define MAS3_SPSIZE_SHIFT 1
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#define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK
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#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
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#define MAS4_INDD 0x00008000 /* Default IND */
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#define MAS4_TSIZED(x) MAS1_TSIZE(x)
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#define MAS4_X0D 0x00000040
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#define MAS4_X1D 0x00000020
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#define MAS4_WD 0x00000010
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#define MAS4_ID 0x00000008
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#define MAS4_MD 0x00000004
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#define MAS4_GD 0x00000002
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#define MAS4_ED 0x00000001
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#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
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#define MAS4_WIMGED_SHIFT 0
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#define MAS4_VLED MAS4_X1D /* Default VLE */
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#define MAS4_ACMD 0x000000c0 /* Default ACM */
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#define MAS4_ACMD_SHIFT 6
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#define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */
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#define MAS4_TSIZED_SHIFT 7
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#define MAS5_SGS 0x80000000
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#define MAS6_SPID0 0x3FFF0000
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#define MAS6_SPID1 0x00007FFE
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#define MAS6_ISIZE(x) MAS1_TSIZE(x)
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#define MAS6_SAS 0x00000001
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#define MAS6_SPID MAS6_SPID0
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#define MAS6_SIND 0x00000002 /* Indirect page */
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#define MAS6_SIND_SHIFT 1
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#define MAS6_SPID_MASK 0x3fff0000
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#define MAS6_SPID_SHIFT 16
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#define MAS6_ISIZE_MASK 0x00000f80
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#define MAS6_ISIZE_SHIFT 7
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#define MAS7_RPN 0xFFFFFFFF
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#define MAS8_TGS 0x80000000 /* Guest space */
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#define MAS8_VF 0x40000000 /* Virtualization Fault */
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#define MAS8_TLPID 0x000000ff
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/* Bit definitions for MMUCFG */
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#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
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#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
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#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
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#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
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#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
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#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
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#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
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#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
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#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
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/* Bit definitions for MMUCSR0 */
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#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
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#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
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#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
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#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
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#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
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#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
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#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
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/* MMUCFG bits */
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#define MMUCFG_MAVN_NASK 0x00000003
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#define MMUCFG_MAVN_V1_0 0x00000000
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#define MMUCFG_MAVN_V2_0 0x00000001
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#define MMUCFG_NTLB_MASK 0x0000000c
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#define MMUCFG_NTLB_SHIFT 2
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#define MMUCFG_PIDSIZE_MASK 0x000007c0
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#define MMUCFG_PIDSIZE_SHIFT 6
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#define MMUCFG_TWC 0x00008000
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#define MMUCFG_LRAT 0x00010000
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#define MMUCFG_RASIZE_MASK 0x00fe0000
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#define MMUCFG_RASIZE_SHIFT 17
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#define MMUCFG_LPIDSIZE_MASK 0x0f000000
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#define MMUCFG_LPIDSIZE_SHIFT 24
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/* TLBnCFG encoding */
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#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
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#define TLBnCFG_HES 0x00002000 /* HW select supported */
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#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
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#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
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#define TLBnCFG_IND 0x00020000 /* IND entries supported */
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#define TLBnCFG_PT 0x00040000 /* Can load from page table */
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#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
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#define TLBnCFG_MINSIZE_SHIFT 20
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#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
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#define TLBnCFG_MAXSIZE_SHIFT 16
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#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
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#define TLBnCFG_ASSOC_SHIFT 24
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/* TLBnPS encoding */
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#define TLBnPS_4K 0x00000004
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#define TLBnPS_8K 0x00000008
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#define TLBnPS_16K 0x00000010
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#define TLBnPS_32K 0x00000020
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#define TLBnPS_64K 0x00000040
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#define TLBnPS_128K 0x00000080
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#define TLBnPS_256K 0x00000100
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#define TLBnPS_512K 0x00000200
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#define TLBnPS_1M 0x00000400
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#define TLBnPS_2M 0x00000800
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#define TLBnPS_4M 0x00001000
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#define TLBnPS_8M 0x00002000
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#define TLBnPS_16M 0x00004000
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#define TLBnPS_32M 0x00008000
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#define TLBnPS_64M 0x00010000
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#define TLBnPS_128M 0x00020000
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#define TLBnPS_256M 0x00040000
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#define TLBnPS_512M 0x00080000
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#define TLBnPS_1G 0x00100000
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#define TLBnPS_2G 0x00200000
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#define TLBnPS_4G 0x00400000
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#define TLBnPS_8G 0x00800000
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#define TLBnPS_16G 0x01000000
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#define TLBnPS_32G 0x02000000
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#define TLBnPS_64G 0x04000000
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#define TLBnPS_128G 0x08000000
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#define TLBnPS_256G 0x10000000
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/* tlbilx action encoding */
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#define TLBILX_T_ALL 0
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#define TLBILX_T_TID 1
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#define TLBILX_T_FULLMATCH 3
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#define TLBILX_T_CLASS0 4
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#define TLBILX_T_CLASS1 5
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#define TLBILX_T_CLASS2 6
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#define TLBILX_T_CLASS3 7
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/*
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* The mapping only needs to be cache-coherent on SMP, except on
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* Freescale e500mc derivatives where it's also needed for coherent DMA.
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*/
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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#define MAS2_M_IF_NEEDED MAS2_M
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#else
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#define MAS2_M_IF_NEEDED 0
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/bug.h>
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extern unsigned int tlbcam_index;
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typedef struct {
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unsigned int id;
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unsigned int active;
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void __user *vdso;
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} mm_context_t;
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/* Page size definitions, common between 32 and 64-bit
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* penc : is the pte encoding mask
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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unsigned int enc; /* PTE encoding */
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unsigned int ind; /* Corresponding indirect page size shift */
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unsigned int flags;
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#define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
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#define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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static inline int shift_to_mmu_psize(unsigned int shift)
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{
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int psize;
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for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
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if (mmu_psize_defs[psize].shift == shift)
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return psize;
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return -1;
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}
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static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
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{
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if (mmu_psize_defs[mmu_psize].shift)
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return mmu_psize_defs[mmu_psize].shift;
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BUG();
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}
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/* The page sizes use the same names as 64-bit hash but are
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* constants
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*/
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#if defined(CONFIG_PPC_4K_PAGES)
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#define mmu_virtual_psize MMU_PAGE_4K
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#else
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#error Unsupported page size
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#endif
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extern int mmu_linear_psize;
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extern int mmu_vmemmap_psize;
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struct tlb_core_data {
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/*
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* Per-core spinlock for e6500 TLB handlers (no tlbsrx.)
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* Must be the first struct element.
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*/
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u8 lock;
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/* For software way selection, as on Freescale TLB1 */
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u8 esel_next, esel_max, esel_first;
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};
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#ifdef CONFIG_PPC64
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extern unsigned long linear_map_top;
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extern int book3e_htw_mode;
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#define PPC_HTW_NONE 0
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#define PPC_HTW_IBM 1
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#define PPC_HTW_E6500 2
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/*
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* 64-bit booke platforms don't load the tlb in the tlb miss handler code.
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* HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
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* return 1, indicating that the tlb requires preloading.
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*/
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#define HUGETLB_NEED_PRELOAD
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#define mmu_cleanup_all NULL
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#define MAX_PHYSMEM_BITS 44
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#endif
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#endif /* !__ASSEMBLY__ */
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||
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#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
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