324 lines
10 KiB
C
324 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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* Rewrite, cleanup:
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*/
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#ifndef _ASM_IOMMU_H
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#define _ASM_IOMMU_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-map-ops.h>
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#include <linux/bitops.h>
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#include <asm/machdep.h>
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#include <asm/types.h>
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#include <asm/pci-bridge.h>
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#include <asm/asm-const.h>
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#define IOMMU_PAGE_SHIFT_4K 12
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#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
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#define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
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#define IOMMU_PAGE_ALIGN_4K(addr) ALIGN(addr, IOMMU_PAGE_SIZE_4K)
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#define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
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#define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
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#define IOMMU_PAGE_ALIGN(addr, tblptr) ALIGN(addr, IOMMU_PAGE_SIZE(tblptr))
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/* Boot time flags */
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extern int iommu_is_off;
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extern int iommu_force_on;
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struct iommu_table_ops {
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/*
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* When called with direction==DMA_NONE, it is equal to clear().
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* uaddr is a linear map address.
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*/
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int (*set)(struct iommu_table *tbl,
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long index, long npages,
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unsigned long uaddr,
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enum dma_data_direction direction,
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unsigned long attrs);
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#ifdef CONFIG_IOMMU_API
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/*
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* Exchanges existing TCE with new TCE plus direction bits;
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* returns old TCE and DMA direction mask.
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* @tce is a physical address.
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*/
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int (*xchg_no_kill)(struct iommu_table *tbl,
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long index,
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unsigned long *hpa,
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enum dma_data_direction *direction,
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bool realmode);
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void (*tce_kill)(struct iommu_table *tbl,
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unsigned long index,
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unsigned long pages,
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bool realmode);
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__be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc);
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#endif
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void (*clear)(struct iommu_table *tbl,
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long index, long npages);
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/* get() returns a physical address */
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unsigned long (*get)(struct iommu_table *tbl, long index);
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void (*flush)(struct iommu_table *tbl);
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void (*free)(struct iommu_table *tbl);
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};
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/* These are used by VIO */
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extern struct iommu_table_ops iommu_table_lpar_multi_ops;
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extern struct iommu_table_ops iommu_table_pseries_ops;
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/*
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* IOMAP_MAX_ORDER defines the largest contiguous block
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* of dma space we can get. IOMAP_MAX_ORDER = 13
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* allows up to 2**12 pages (4096 * 4096) = 16 MB
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*/
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#define IOMAP_MAX_ORDER 13
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#define IOMMU_POOL_HASHBITS 2
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#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
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struct iommu_pool {
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unsigned long start;
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unsigned long end;
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unsigned long hint;
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spinlock_t lock;
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} ____cacheline_aligned_in_smp;
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struct iommu_table {
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unsigned long it_busno; /* Bus number this table belongs to */
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unsigned long it_size; /* Size of iommu table in entries */
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unsigned long it_indirect_levels;
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unsigned long it_level_size;
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unsigned long it_allocated_size;
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unsigned long it_offset; /* Offset into global table */
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unsigned long it_base; /* mapped address of tce table */
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unsigned long it_index; /* which iommu table this is */
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unsigned long it_type; /* type: PCI or Virtual Bus */
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unsigned long it_blocksize; /* Entries in each block (cacheline) */
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unsigned long poolsize;
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unsigned long nr_pools;
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struct iommu_pool large_pool;
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struct iommu_pool pools[IOMMU_NR_POOLS];
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unsigned long *it_map; /* A simple allocation bitmap for now */
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unsigned long it_page_shift;/* table iommu page size */
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struct list_head it_group_list;/* List of iommu_table_group_link */
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__be64 *it_userspace; /* userspace view of the table */
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struct iommu_table_ops *it_ops;
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struct kref it_kref;
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int it_nid;
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unsigned long it_reserved_start; /* Start of not-DMA-able (MMIO) area */
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unsigned long it_reserved_end;
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};
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#define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \
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((tbl)->it_ops->useraddrptr((tbl), (entry), false))
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#define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
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((tbl)->it_ops->useraddrptr((tbl), (entry), true))
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/* Pure 2^n version of get_order */
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static inline __attribute_const__
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int get_iommu_order(unsigned long size, struct iommu_table *tbl)
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{
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return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
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}
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struct scatterlist;
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#ifdef CONFIG_PPC64
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static inline void set_iommu_table_base(struct device *dev,
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struct iommu_table *base)
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{
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dev->archdata.iommu_table_base = base;
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}
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static inline void *get_iommu_table_base(struct device *dev)
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{
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return dev->archdata.iommu_table_base;
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}
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extern int dma_iommu_dma_supported(struct device *dev, u64 mask);
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extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl);
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extern int iommu_tce_table_put(struct iommu_table *tbl);
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/* Initializes an iommu_table based in values set in the passed-in
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* structure
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*/
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extern struct iommu_table *iommu_init_table(struct iommu_table *tbl,
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int nid, unsigned long res_start, unsigned long res_end);
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bool iommu_table_in_use(struct iommu_table *tbl);
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#define IOMMU_TABLE_GROUP_MAX_TABLES 2
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struct iommu_table_group;
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struct iommu_table_group_ops {
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unsigned long (*get_table_size)(
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__u32 page_shift,
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__u64 window_size,
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__u32 levels);
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long (*create_table)(struct iommu_table_group *table_group,
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int num,
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__u32 page_shift,
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__u64 window_size,
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__u32 levels,
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struct iommu_table **ptbl);
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long (*set_window)(struct iommu_table_group *table_group,
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int num,
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struct iommu_table *tblnew);
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long (*unset_window)(struct iommu_table_group *table_group,
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int num);
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/* Switch ownership from platform code to external user (e.g. VFIO) */
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void (*take_ownership)(struct iommu_table_group *table_group);
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/* Switch ownership from external user (e.g. VFIO) back to core */
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void (*release_ownership)(struct iommu_table_group *table_group);
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};
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struct iommu_table_group_link {
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struct list_head next;
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struct rcu_head rcu;
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struct iommu_table_group *table_group;
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};
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struct iommu_table_group {
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/* IOMMU properties */
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__u32 tce32_start;
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__u32 tce32_size;
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__u64 pgsizes; /* Bitmap of supported page sizes */
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__u32 max_dynamic_windows_supported;
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__u32 max_levels;
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struct iommu_group *group;
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struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
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struct iommu_table_group_ops *ops;
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};
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#ifdef CONFIG_IOMMU_API
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extern void iommu_register_group(struct iommu_table_group *table_group,
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int pci_domain_number, unsigned long pe_num);
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extern int iommu_add_device(struct iommu_table_group *table_group,
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struct device *dev);
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extern void iommu_del_device(struct device *dev);
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extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl,
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unsigned long entry, unsigned long *hpa,
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enum dma_data_direction *direction);
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extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
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struct iommu_table *tbl,
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unsigned long entry, unsigned long *hpa,
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enum dma_data_direction *direction);
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extern void iommu_tce_kill(struct iommu_table *tbl,
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unsigned long entry, unsigned long pages);
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#else
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static inline void iommu_register_group(struct iommu_table_group *table_group,
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int pci_domain_number,
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unsigned long pe_num)
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{
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}
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static inline int iommu_add_device(struct iommu_table_group *table_group,
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struct device *dev)
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{
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return 0;
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}
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static inline void iommu_del_device(struct device *dev)
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{
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}
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#endif /* !CONFIG_IOMMU_API */
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u64 dma_iommu_get_required_mask(struct device *dev);
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#else
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static inline void *get_iommu_table_base(struct device *dev)
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{
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return NULL;
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}
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static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
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{
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return 0;
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}
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#endif /* CONFIG_PPC64 */
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extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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struct scatterlist *sglist, int nelems,
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unsigned long mask,
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enum dma_data_direction direction,
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unsigned long attrs);
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extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
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struct scatterlist *sglist,
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int nelems,
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enum dma_data_direction direction,
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unsigned long attrs);
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extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
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size_t size, dma_addr_t *dma_handle,
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unsigned long mask, gfp_t flag, int node);
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extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
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struct page *page, unsigned long offset,
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size_t size, unsigned long mask,
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enum dma_data_direction direction,
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unsigned long attrs);
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extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction,
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unsigned long attrs);
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void __init iommu_init_early_pSeries(void);
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extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
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extern void iommu_init_early_pasemi(void);
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#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
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static inline void iommu_restore(void)
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{
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if (ppc_md.iommu_restore)
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ppc_md.iommu_restore();
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}
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#endif
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/* The API to support IOMMU operations for VFIO */
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extern int iommu_tce_check_ioba(unsigned long page_shift,
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unsigned long offset, unsigned long size,
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unsigned long ioba, unsigned long npages);
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extern int iommu_tce_check_gpa(unsigned long page_shift,
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unsigned long gpa);
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#define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \
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(iommu_tce_check_ioba((tbl)->it_page_shift, \
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(tbl)->it_offset, (tbl)->it_size, \
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(ioba), (npages)) || (tce_value))
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#define iommu_tce_put_param_check(tbl, ioba, gpa) \
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(iommu_tce_check_ioba((tbl)->it_page_shift, \
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(tbl)->it_offset, (tbl)->it_size, \
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(ioba), 1) || \
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iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
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extern void iommu_flush_tce(struct iommu_table *tbl);
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extern int iommu_take_ownership(struct iommu_table *tbl);
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extern void iommu_release_ownership(struct iommu_table *tbl);
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extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
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extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
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#ifdef CONFIG_PPC_CELL_NATIVE
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extern bool iommu_fixed_is_weak;
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#else
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#define iommu_fixed_is_weak false
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#endif
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extern const struct dma_map_ops dma_iommu_ops;
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#endif /* __KERNEL__ */
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#endif /* _ASM_IOMMU_H */
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