324 lines
10 KiB
C
324 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_PGTABLE_RADIX_H
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#define _ASM_POWERPC_PGTABLE_RADIX_H
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#include <asm/asm-const.h>
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#ifndef __ASSEMBLY__
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#include <asm/cmpxchg.h>
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#endif
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/book3s/64/radix-64k.h>
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#else
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#include <asm/book3s/64/radix-4k.h>
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/book3s/64/tlbflush-radix.h>
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#include <asm/cpu_has_feature.h>
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#endif
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/* An empty PTE can still have a R or C writeback */
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#define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
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/* Bits to set in a RPMD/RPUD/RPGD */
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#define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
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#define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
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#define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
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/* Don't have anything in the reserved bits and leaf bits */
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#define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
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#define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
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#define RADIX_P4D_BAD_BITS 0x60000000000000e0UL
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#define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
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#define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
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#define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
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/*
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* Size of EA range mapped by our pagetables.
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*/
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#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
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RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
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#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
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/*
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* We support 52 bit address space, Use top bit for kernel
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* virtual mapping. Also make sure kernel fit in the top
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* quadrant.
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*
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* +------------------+
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* +------------------+ Kernel virtual map (0xc008000000000000)
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* | |
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* | |
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* | |
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* 0b11......+------------------+ Kernel linear map (0xc....)
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* | |
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* | 2 quadrant |
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* | |
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* 0b10......+------------------+
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* | |
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* | 1 quadrant |
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* | |
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* 0b01......+------------------+
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* | |
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* | 0 quadrant |
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* | |
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* 0b00......+------------------+
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*
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*
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* 3rd quadrant expanded:
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* +------------------------------+
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* | |
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* | |
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* | |
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* +------------------------------+ Kernel vmemmap end (0xc010000000000000)
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* | |
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* | 512TB |
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* | |
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* +------------------------------+ Kernel IO map end/vmemap start
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* | |
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* | 512TB |
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* | |
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* +------------------------------+ Kernel vmap end/ IO map start
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* | |
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* | 512TB |
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* | |
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* +------------------------------+ Kernel virt start (0xc008000000000000)
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* | |
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* | |
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* | |
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* +------------------------------+ Kernel linear (0xc.....)
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*/
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/*
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* If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
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* if we increase SECTIONS_WIDTH we will not store node details in page->flags and
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* page_to_nid does a page->section->node lookup
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* Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
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* memory requirements with large number of sections.
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* 51 bits is the max physical real address on POWER9
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*/
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#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME)
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#define R_MAX_PHYSMEM_BITS 51
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#else
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#define R_MAX_PHYSMEM_BITS 46
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#endif
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#define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
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/*
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* 49 = MAX_EA_BITS_PER_CONTEXT (hash specific). To make sure we pick
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* the same value as hash.
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*/
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#define RADIX_KERN_MAP_SIZE (1UL << 49)
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#define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
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#define RADIX_VMALLOC_SIZE RADIX_KERN_MAP_SIZE
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#define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
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#define RADIX_KERN_IO_START RADIX_VMALLOC_END
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#define RADIX_KERN_IO_SIZE RADIX_KERN_MAP_SIZE
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#define RADIX_KERN_IO_END (RADIX_KERN_IO_START + RADIX_KERN_IO_SIZE)
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#define RADIX_VMEMMAP_START RADIX_KERN_IO_END
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#define RADIX_VMEMMAP_SIZE RADIX_KERN_MAP_SIZE
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#define RADIX_VMEMMAP_END (RADIX_VMEMMAP_START + RADIX_VMEMMAP_SIZE)
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#ifndef __ASSEMBLY__
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#define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
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#define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
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#define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
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#define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
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#ifdef CONFIG_STRICT_KERNEL_RWX
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extern void radix__mark_rodata_ro(void);
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extern void radix__mark_initmem_nx(void);
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#endif
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extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
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pte_t entry, unsigned long address,
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int psize);
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extern void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t pte);
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static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
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unsigned long set)
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{
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__be64 old_be, tmp_be;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # pte_update\n"
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" andc %1,%0,%5 \n"
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" or %1,%1,%4 \n"
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" stdcx. %1,0,%3 \n"
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" bne- 1b"
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: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
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: "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
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: "cc" );
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return be64_to_cpu(old_be);
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}
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static inline unsigned long radix__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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{
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unsigned long old_pte;
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old_pte = __radix_pte_update(ptep, clr, set);
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if (!huge)
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assert_pte_locked(mm, addr);
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return old_pte;
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}
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static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, int full)
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{
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unsigned long old_pte;
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if (full) {
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old_pte = pte_val(*ptep);
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*ptep = __pte(0);
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} else
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old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
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return __pte(old_pte);
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}
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static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
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{
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return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
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}
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static inline int radix__pte_none(pte_t pte)
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{
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return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
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}
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static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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*ptep = pte;
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/*
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* The architecture suggests a ptesync after setting the pte, which
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* orders the store that updates the pte with subsequent page table
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* walk accesses which may load the pte. Without this it may be
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* possible for a subsequent access to result in spurious fault.
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*
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* This is not necessary for correctness, because a spurious fault
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* is tolerated by the page fault handler, and this store will
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* eventually be seen. In testing, there was no noticable increase
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* in user faults on POWER9. Avoiding ptesync here is a significant
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* win for things like fork. If a future microarchitecture benefits
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* from ptesync, it should probably go into update_mmu_cache, rather
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* than set_pte_at (which is used to set ptes unrelated to faults).
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*
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* Spurious faults from the kernel memory are not tolerated, so there
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* is a ptesync in flush_cache_vmap, and __map_kernel_page() follows
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* the pte update sequence from ISA Book III 6.10 Translation Table
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* Update Synchronization Requirements.
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*/
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}
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static inline int radix__pmd_bad(pmd_t pmd)
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{
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return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
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}
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static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
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{
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return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
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}
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static inline int radix__pud_bad(pud_t pud)
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{
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return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
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}
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static inline int radix__p4d_bad(p4d_t p4d)
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{
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return !!(p4d_val(p4d) & RADIX_P4D_BAD_BITS);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static inline int radix__pmd_trans_huge(pmd_t pmd)
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{
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return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
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}
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static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) | _PAGE_PTE);
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}
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extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, unsigned long clr,
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unsigned long set);
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extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable);
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extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
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extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp);
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static inline int radix__has_transparent_hugepage(void)
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{
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/* For radix 2M at PMD level means thp */
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if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
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return 1;
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return 0;
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}
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#endif
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static inline pmd_t radix__pmd_mkdevmap(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
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}
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extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
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unsigned long page_size,
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unsigned long phys);
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extern void radix__vmemmap_remove_mapping(unsigned long start,
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unsigned long page_size);
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extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
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pgprot_t flags, unsigned int psz);
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static inline unsigned long radix__get_tree_size(void)
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{
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unsigned long rts_field;
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/*
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* We support 52 bits, hence:
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* bits 52 - 31 = 21, 0b10101
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* RTS encoding details
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* bits 0 - 3 of rts -> bits 6 - 8 unsigned long
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* bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
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*/
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rts_field = (0x5UL << 5); /* 6 - 8 bits */
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rts_field |= (0x2UL << 61);
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return rts_field;
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}
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#ifdef CONFIG_MEMORY_HOTPLUG
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int radix__create_section_mapping(unsigned long start, unsigned long end,
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int nid, pgprot_t prot);
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int radix__remove_section_mapping(unsigned long start, unsigned long end);
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#endif /* CONFIG_MEMORY_HOTPLUG */
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void radix__kernel_map_pages(struct page *page, int numpages, int enable);
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#endif /* __ASSEMBLY__ */
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#endif
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