259 lines
7.5 KiB
C
259 lines
7.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_H
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#ifdef __KERNEL__
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#include <asm/asm-const.h>
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/*
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* Common bits between 4K and 64K pages in a linux-style PTE.
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* Additional bits may be defined in pgtable-hash64-*.h
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*
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*/
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#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/book3s/64/hash-64k.h>
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#else
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#include <asm/book3s/64/hash-4k.h>
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#endif
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/* Bits to set in a PMD/PUD/PGD entry valid bit*/
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#define HASH_PMD_VAL_BITS (0x8000000000000000UL)
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#define HASH_PUD_VAL_BITS (0x8000000000000000UL)
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#define HASH_PGD_VAL_BITS (0x8000000000000000UL)
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/*
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* Size of EA range mapped by our pagetables.
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*/
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#define H_PGTABLE_EADDR_SIZE (H_PTE_INDEX_SIZE + H_PMD_INDEX_SIZE + \
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H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
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#define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
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/*
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* Top 2 bits are ignored in page table walk.
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*/
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#define EA_MASK (~(0xcUL << 60))
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/*
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* We store the slot details in the second half of page table.
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* Increase the pud level table so that hugetlb ptes can be stored
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* at pud level.
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*/
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#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_64K_PAGES)
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#define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE + 1)
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#else
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#define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE)
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#endif
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/*
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* +------------------------------+
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* | |
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* | |
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* | |
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* +------------------------------+ Kernel virtual map end (0xc00e000000000000)
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* | |
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* | |
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* | 512TB/16TB of vmemmap |
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* | |
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* | |
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* +------------------------------+ Kernel vmemmap start
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* | |
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* | 512TB/16TB of IO map |
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* | |
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* +------------------------------+ Kernel IO map start
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* | |
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* | 512TB/16TB of vmap |
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* | |
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* +------------------------------+ Kernel virt start (0xc008000000000000)
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* | |
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* | |
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* | |
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* +------------------------------+ Kernel linear (0xc.....)
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*/
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#define H_VMALLOC_START H_KERN_VIRT_START
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#define H_VMALLOC_SIZE H_KERN_MAP_SIZE
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#define H_VMALLOC_END (H_VMALLOC_START + H_VMALLOC_SIZE)
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#define H_KERN_IO_START H_VMALLOC_END
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#define H_KERN_IO_SIZE H_KERN_MAP_SIZE
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#define H_KERN_IO_END (H_KERN_IO_START + H_KERN_IO_SIZE)
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#define H_VMEMMAP_START H_KERN_IO_END
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#define H_VMEMMAP_SIZE H_KERN_MAP_SIZE
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#define H_VMEMMAP_END (H_VMEMMAP_START + H_VMEMMAP_SIZE)
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#define NON_LINEAR_REGION_ID(ea) ((((unsigned long)ea - H_KERN_VIRT_START) >> REGION_SHIFT) + 2)
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/*
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* Region IDs
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*/
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#define USER_REGION_ID 0
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#define LINEAR_MAP_REGION_ID 1
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#define VMALLOC_REGION_ID NON_LINEAR_REGION_ID(H_VMALLOC_START)
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#define IO_REGION_ID NON_LINEAR_REGION_ID(H_KERN_IO_START)
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#define VMEMMAP_REGION_ID NON_LINEAR_REGION_ID(H_VMEMMAP_START)
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#define INVALID_REGION_ID (VMEMMAP_REGION_ID + 1)
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/*
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* Defines the address of the vmemap area, in its own region on
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* hash table CPUs.
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*/
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/* PTEIDX nibble */
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#define _PTEIDX_SECONDARY 0x8
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#define _PTEIDX_GROUP_IX 0x7
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#define H_PMD_BAD_BITS (PTE_TABLE_SIZE-1)
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#define H_PUD_BAD_BITS (PMD_TABLE_SIZE-1)
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#ifndef __ASSEMBLY__
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static inline int get_region_id(unsigned long ea)
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{
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int region_id;
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int id = (ea >> 60UL);
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if (id == 0)
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return USER_REGION_ID;
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if (id != (PAGE_OFFSET >> 60))
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return INVALID_REGION_ID;
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if (ea < H_KERN_VIRT_START)
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return LINEAR_MAP_REGION_ID;
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BUILD_BUG_ON(NON_LINEAR_REGION_ID(H_VMALLOC_START) != 2);
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region_id = NON_LINEAR_REGION_ID(ea);
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return region_id;
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}
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#define hash__pmd_bad(pmd) (pmd_val(pmd) & H_PMD_BAD_BITS)
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#define hash__pud_bad(pud) (pud_val(pud) & H_PUD_BAD_BITS)
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static inline int hash__p4d_bad(p4d_t p4d)
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{
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return (p4d_val(p4d) == 0);
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}
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#ifdef CONFIG_STRICT_KERNEL_RWX
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extern void hash__mark_rodata_ro(void);
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extern void hash__mark_initmem_nx(void);
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#endif
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags);
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/* Atomic PTE updates */
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static inline unsigned long hash__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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{
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__be64 old_be, tmp_be;
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unsigned long old;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # pte_update\n\
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and. %1,%0,%6\n\
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bne- 1b \n\
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andc %1,%0,%4 \n\
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or %1,%1,%7\n\
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stdcx. %1,0,%3 \n\
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bne- 1b"
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: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
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: "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep),
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"r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
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: "cc" );
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/* huge pages use the old page table lock */
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if (!huge)
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assert_pte_locked(mm, addr);
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old = be64_to_cpu(old_be);
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if (old & H_PAGE_HASHPTE)
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hpte_need_flush(mm, addr, ptep, old, huge);
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return old;
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}
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/* Set the dirty and/or accessed bits atomically in a linux PTE, this
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* function doesn't need to flush the hash entry
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*/
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static inline void hash__ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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__be64 old, tmp, val, mask;
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mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE |
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_PAGE_EXEC | _PAGE_SOFT_DIRTY);
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val = pte_raw(entry) & mask;
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__asm__ __volatile__(
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"1: ldarx %0,0,%4\n\
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and. %1,%0,%6\n\
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bne- 1b \n\
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or %0,%3,%0\n\
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stdcx. %0,0,%4\n\
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bne- 1b"
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:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
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:"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY))
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:"cc");
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}
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static inline int hash__pte_same(pte_t pte_a, pte_t pte_b)
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{
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return (((pte_raw(pte_a) ^ pte_raw(pte_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
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}
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static inline int hash__pte_none(pte_t pte)
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{
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return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;
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}
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unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
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int ssize, real_pte_t rpte, unsigned int subpg_index);
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void hash__set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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/*
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* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 32-bit PTEs.
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*/
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*ptep = pte;
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, unsigned long old_pmd);
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#else
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static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp,
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unsigned long old_pmd)
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{
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WARN(1, "%s called with THP disabled\n", __func__);
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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int hash__map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot);
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extern int __meminit hash__vmemmap_create_mapping(unsigned long start,
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unsigned long page_size,
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unsigned long phys);
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extern void hash__vmemmap_remove_mapping(unsigned long start,
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unsigned long page_size);
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int hash__create_section_mapping(unsigned long start, unsigned long end,
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int nid, pgprot_t prot);
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int hash__remove_section_mapping(unsigned long start, unsigned long end);
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void hash__kernel_map_pages(struct page *page, int numpages, int enable);
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */
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