237 lines
6.1 KiB
C
237 lines
6.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
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#define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
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/*
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* 32-bit hash table MMU support
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*/
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/*
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* BATs
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*/
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/* Block size masks */
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#define BL_128K 0x000
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#define BL_256K 0x001
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#define BL_512K 0x003
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#define BL_1M 0x007
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#define BL_2M 0x00F
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#define BL_4M 0x01F
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#define BL_8M 0x03F
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#define BL_16M 0x07F
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#define BL_32M 0x0FF
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#define BL_64M 0x1FF
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#define BL_128M 0x3FF
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#define BL_256M 0x7FF
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/* BAT Access Protection */
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#define BPP_XX 0x00 /* No access */
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#define BPP_RX 0x01 /* Read only */
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#define BPP_RW 0x02 /* Read/write */
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#ifndef __ASSEMBLY__
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/* Contort a phys_addr_t into the right format/bits for a BAT */
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#ifdef CONFIG_PHYS_64BIT
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#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
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((x & 0x0000000e00000000ULL) >> 24) | \
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((x & 0x0000000100000000ULL) >> 30)))
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#define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
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(((u64)(x) << 24) & 0x0000000e00000000ULL) | \
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(((u64)(x) << 30) & 0x0000000100000000ULL))
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#else
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#define BAT_PHYS_ADDR(x) (x)
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#define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
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#endif
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struct ppc_bat {
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u32 batu;
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u32 batl;
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};
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#endif /* !__ASSEMBLY__ */
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/*
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* Hash table
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*/
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/* Values for PP (assumes Ks=0, Kp=1) */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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/* Values for Segment Registers */
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#define SR_NX 0x10000000 /* No Execute */
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#define SR_KP 0x20000000 /* User key */
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#define SR_KS 0x40000000 /* Supervisor key */
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#ifdef __ASSEMBLY__
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#include <asm/asm-offsets.h>
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.macro uus_addi sr reg1 reg2 imm
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.if NUM_USER_SEGMENTS > \sr
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addi \reg1,\reg2,\imm
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.endif
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.endm
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.macro uus_mtsr sr reg1
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.if NUM_USER_SEGMENTS > \sr
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mtsr \sr, \reg1
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.endif
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.endm
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/*
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* This isync() shouldn't be necessary as the kernel is not excepted to run
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* any instruction in userspace soon after the update of segments and 'rfi'
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* instruction is used to return to userspace, but hash based cores
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* (at least G3) seem to exhibit a random behaviour when the 'isync' is not
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* there. 603 cores don't have this behaviour so don't do the 'isync' as it
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* saves several CPU cycles.
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*/
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.macro uus_isync
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#ifdef CONFIG_PPC_BOOK3S_604
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BEGIN_MMU_FTR_SECTION
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isync
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
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#endif
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.endm
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.macro update_user_segments_by_4 tmp1 tmp2 tmp3 tmp4
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uus_addi 1, \tmp2, \tmp1, 0x111
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uus_addi 2, \tmp3, \tmp1, 0x222
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uus_addi 3, \tmp4, \tmp1, 0x333
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uus_mtsr 0, \tmp1
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uus_mtsr 1, \tmp2
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uus_mtsr 2, \tmp3
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uus_mtsr 3, \tmp4
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uus_addi 4, \tmp1, \tmp1, 0x444
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uus_addi 5, \tmp2, \tmp2, 0x444
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uus_addi 6, \tmp3, \tmp3, 0x444
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uus_addi 7, \tmp4, \tmp4, 0x444
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uus_mtsr 4, \tmp1
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uus_mtsr 5, \tmp2
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uus_mtsr 6, \tmp3
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uus_mtsr 7, \tmp4
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uus_addi 8, \tmp1, \tmp1, 0x444
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uus_addi 9, \tmp2, \tmp2, 0x444
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uus_addi 10, \tmp3, \tmp3, 0x444
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uus_addi 11, \tmp4, \tmp4, 0x444
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uus_mtsr 8, \tmp1
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uus_mtsr 9, \tmp2
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uus_mtsr 10, \tmp3
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uus_mtsr 11, \tmp4
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uus_addi 12, \tmp1, \tmp1, 0x444
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uus_addi 13, \tmp2, \tmp2, 0x444
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uus_addi 14, \tmp3, \tmp3, 0x444
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uus_addi 15, \tmp4, \tmp4, 0x444
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uus_mtsr 12, \tmp1
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uus_mtsr 13, \tmp2
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uus_mtsr 14, \tmp3
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uus_mtsr 15, \tmp4
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uus_isync
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.endm
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#else
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/*
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* This macro defines the mapping from contexts to VSIDs (virtual
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* segment IDs). We use a skew on both the context and the high 4 bits
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* of the 32-bit virtual address (the "effective segment ID") in order
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* to spread out the entries in the MMU hash table. Note, if this
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* function is changed then hash functions will have to be
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* changed to correspond.
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*/
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#define CTX_TO_VSID(c, id) ((((c) * (897 * 16)) + (id * 0x111)) & 0xffffff)
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/*
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* Hardware Page Table Entry
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* Note that the xpn and x bitfields are used only by processors that
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* support extended addressing; otherwise, those bits are reserved.
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*/
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struct hash_pte {
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unsigned long v:1; /* Entry is valid */
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unsigned long vsid:24; /* Virtual segment identifier */
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unsigned long h:1; /* Hash algorithm indicator */
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unsigned long api:6; /* Abbreviated page index */
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unsigned long rpn:20; /* Real (physical) page number */
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unsigned long xpn:3; /* Real page number bits 0-2, optional */
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unsigned long r:1; /* Referenced */
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unsigned long c:1; /* Changed */
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unsigned long w:1; /* Write-thru cache mode */
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unsigned long i:1; /* Cache inhibited */
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unsigned long m:1; /* Memory coherence */
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unsigned long g:1; /* Guarded */
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unsigned long x:1; /* Real page number bit 3, optional */
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unsigned long pp:2; /* Page protection */
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};
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typedef struct {
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unsigned long id;
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unsigned long sr0;
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void __user *vdso;
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} mm_context_t;
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#ifdef CONFIG_PPC_KUEP
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#define INIT_MM_CONTEXT(mm) .context.sr0 = SR_NX
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#endif
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void update_bats(void);
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static inline void cleanup_cpu_mmu_context(void) { }
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/* patch sites */
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extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
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extern s32 patch__hash_page_B, patch__hash_page_C;
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extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
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extern s32 patch__flush_hash_B;
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#include <asm/reg.h>
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#include <asm/task_size_32.h>
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static __always_inline void update_user_segment(u32 n, u32 val)
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{
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if (n << 28 < TASK_SIZE)
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mtsr(val + n * 0x111, n << 28);
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}
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static __always_inline void update_user_segments(u32 val)
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{
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val &= 0xf0ffffff;
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update_user_segment(0, val);
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update_user_segment(1, val);
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update_user_segment(2, val);
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update_user_segment(3, val);
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update_user_segment(4, val);
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update_user_segment(5, val);
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update_user_segment(6, val);
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update_user_segment(7, val);
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update_user_segment(8, val);
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update_user_segment(9, val);
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update_user_segment(10, val);
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update_user_segment(11, val);
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update_user_segment(12, val);
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update_user_segment(13, val);
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update_user_segment(14, val);
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update_user_segment(15, val);
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}
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int __init find_free_bat(void);
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unsigned int bat_block_size(unsigned long base, unsigned long top);
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#endif /* !__ASSEMBLY__ */
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/* We happily ignore the smaller BATs on 601, we don't actually use
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* those definitions on hash32 at the moment anyway
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*/
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#define mmu_virtual_psize MMU_PAGE_4K
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#define mmu_linear_psize MMU_PAGE_256M
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#endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */
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