496 lines
14 KiB
C
496 lines
14 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2017 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_H__
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#define __CVMX_H__
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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enum cvmx_mips_space {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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CVMX_MIPS_SPACE_XKPHYS = 2LL,
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CVMX_MIPS_SPACE_XSSEG = 1LL,
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CVMX_MIPS_SPACE_XUSEG = 0LL
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};
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/* These macros for use when using 32 bit pointers. */
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#define CVMX_MIPS32_SPACE_KSEG0 1l
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#define CVMX_ADD_SEG32(segment, add) \
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(((int32_t)segment << 31) | (int32_t)(add))
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#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
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/* These macros simplify the process of creating common IO addresses */
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#define CVMX_ADD_SEG(segment, add) \
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((((uint64_t)segment) << 62) | (add))
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#ifndef CVMX_ADD_IO_SEG
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#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
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#endif
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#include <asm/octeon/cvmx-asm.h>
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#include <asm/octeon/cvmx-packet.h>
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#include <asm/octeon/cvmx-sysinfo.h>
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#include <asm/octeon/cvmx-ciu-defs.h>
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#include <asm/octeon/cvmx-ciu3-defs.h>
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#include <asm/octeon/cvmx-gpio-defs.h>
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#include <asm/octeon/cvmx-iob-defs.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-l2c-defs.h>
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#include <asm/octeon/cvmx-l2d-defs.h>
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#include <asm/octeon/cvmx-l2t-defs.h>
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#include <asm/octeon/cvmx-led-defs.h>
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#include <asm/octeon/cvmx-mio-defs.h>
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#include <asm/octeon/cvmx-pow-defs.h>
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#include <asm/octeon/cvmx-bootinfo.h>
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#include <asm/octeon/cvmx-bootmem.h>
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#include <asm/octeon/cvmx-l2c.h>
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#ifndef CVMX_ENABLE_DEBUG_PRINTS
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#define CVMX_ENABLE_DEBUG_PRINTS 1
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#endif
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#if CVMX_ENABLE_DEBUG_PRINTS
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#define cvmx_dprintf printk
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#else
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#define cvmx_dprintf(...) {}
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#endif
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#define CVMX_MAX_CORES (16)
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#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
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#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
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#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
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#define CAST64(v) ((long long)(long)(v))
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#define CASTPTR(type, v) ((type *)(long)(v))
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/*
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* Returns processor ID, different Linux and simple exec versions
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* provided in the cvmx-app-init*.c files.
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*/
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static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
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static inline uint32_t cvmx_get_proc_id(void)
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{
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uint32_t id;
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asm("mfc0 %0, $15,0" : "=r"(id));
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return id;
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}
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/* turn the variable name into a string */
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#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
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#define CVMX_TMP_STR2(x) #x
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/**
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* Builds a bit mask given the required size in bits.
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*
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* @bits: Number of bits in the mask
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* Returns The mask
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*/ static inline uint64_t cvmx_build_mask(uint64_t bits)
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{
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return ~((~0x0ull) << bits);
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}
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/**
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* Builds a memory address for I/O based on the Major and Sub DID.
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*
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* @major_did: 5 bit major did
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* @sub_did: 3 bit sub did
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* Returns I/O base address
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*/
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static inline uint64_t cvmx_build_io_address(uint64_t major_did,
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uint64_t sub_did)
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{
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return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
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}
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/**
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* Perform mask and shift to place the supplied value into
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* the supplied bit rage.
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*
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* Example: cvmx_build_bits(39,24,value)
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* <pre>
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* 6 5 4 3 3 2 1
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* 3 5 7 9 1 3 5 7 0
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* +-------+-------+-------+-------+-------+-------+-------+------+
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* 000000000000000000000000___________value000000000000000000000000
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* </pre>
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*
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* @high_bit: Highest bit value can occupy (inclusive) 0-63
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* @low_bit: Lowest bit value can occupy inclusive 0-high_bit
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* @value: Value to use
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* Returns Value masked and shifted
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*/
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static inline uint64_t cvmx_build_bits(uint64_t high_bit,
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uint64_t low_bit, uint64_t value)
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{
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return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
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}
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/**
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* Convert a memory pointer (void*) into a hardware compatible
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* memory address (uint64_t). Octeon hardware widgets don't
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* understand logical addresses.
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*
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* @ptr: C style memory pointer
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* Returns Hardware physical address
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*/
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static inline uint64_t cvmx_ptr_to_phys(void *ptr)
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{
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if (sizeof(void *) == 8) {
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/*
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* We're running in 64 bit mode. Normally this means
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* that we can use 40 bits of address space (the
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* hardware limit). Unfortunately there is one case
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* were we need to limit this to 30 bits, sign
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* extended 32 bit. Although these are 64 bits wide,
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* only 30 bits can be used.
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*/
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if ((CAST64(ptr) >> 62) == 3)
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return CAST64(ptr) & cvmx_build_mask(30);
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else
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return CAST64(ptr) & cvmx_build_mask(40);
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} else {
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return (long)(ptr) & 0x1fffffff;
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}
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}
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/**
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* Convert a hardware physical address (uint64_t) into a
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* memory pointer (void *).
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*
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* @physical_address:
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* Hardware physical address to memory
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* Returns Pointer to memory
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*/
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static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
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{
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if (sizeof(void *) == 8) {
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/* Just set the top bit, avoiding any TLB ugliness */
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return CASTPTR(void,
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CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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physical_address));
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} else {
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return CASTPTR(void,
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CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
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physical_address));
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}
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}
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/* The following #if controls the definition of the macro
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CVMX_BUILD_WRITE64. This macro is used to build a store operation to
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a full 64bit address. With a 64bit ABI, this can be done with a simple
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pointer access. 32bit ABIs require more complicated assembly */
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/* We have a full 64bit ABI. Writing to a 64bit address can be done with
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a simple volatile pointer */
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#define CVMX_BUILD_WRITE64(TYPE, ST) \
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static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
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{ \
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*CASTPTR(volatile TYPE##_t, addr) = val; \
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}
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/* The following #if controls the definition of the macro
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CVMX_BUILD_READ64. This macro is used to build a load operation from
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a full 64bit address. With a 64bit ABI, this can be done with a simple
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pointer access. 32bit ABIs require more complicated assembly */
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/* We have a full 64bit ABI. Writing to a 64bit address can be done with
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a simple volatile pointer */
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#define CVMX_BUILD_READ64(TYPE, LT) \
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static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
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{ \
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return *CASTPTR(volatile TYPE##_t, addr); \
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}
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/* The following defines 8 functions for writing to a 64bit address. Each
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takes two arguments, the address and the value to write.
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cvmx_write64_int64 cvmx_write64_uint64
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cvmx_write64_int32 cvmx_write64_uint32
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cvmx_write64_int16 cvmx_write64_uint16
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cvmx_write64_int8 cvmx_write64_uint8 */
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CVMX_BUILD_WRITE64(int64, "sd");
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CVMX_BUILD_WRITE64(int32, "sw");
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CVMX_BUILD_WRITE64(int16, "sh");
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CVMX_BUILD_WRITE64(int8, "sb");
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CVMX_BUILD_WRITE64(uint64, "sd");
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CVMX_BUILD_WRITE64(uint32, "sw");
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CVMX_BUILD_WRITE64(uint16, "sh");
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CVMX_BUILD_WRITE64(uint8, "sb");
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#define cvmx_write64 cvmx_write64_uint64
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/* The following defines 8 functions for reading from a 64bit address. Each
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takes the address as the only argument
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cvmx_read64_int64 cvmx_read64_uint64
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cvmx_read64_int32 cvmx_read64_uint32
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cvmx_read64_int16 cvmx_read64_uint16
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cvmx_read64_int8 cvmx_read64_uint8 */
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CVMX_BUILD_READ64(int64, "ld");
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CVMX_BUILD_READ64(int32, "lw");
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CVMX_BUILD_READ64(int16, "lh");
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CVMX_BUILD_READ64(int8, "lb");
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CVMX_BUILD_READ64(uint64, "ld");
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CVMX_BUILD_READ64(uint32, "lw");
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CVMX_BUILD_READ64(uint16, "lhu");
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CVMX_BUILD_READ64(uint8, "lbu");
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#define cvmx_read64 cvmx_read64_uint64
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static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
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{
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cvmx_write64(csr_addr, val);
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/*
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* Perform an immediate read after every write to an RSL
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* register to force the write to complete. It doesn't matter
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* what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
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* because it is fast and harmless.
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*/
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if (((csr_addr >> 40) & 0x7ffff) == (0x118))
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cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
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}
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static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
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{
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cvmx_write_csr((__force uint64_t)csr_addr, val);
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}
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static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
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{
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cvmx_write64(io_addr, val);
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}
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static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
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{
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uint64_t val = cvmx_read64(csr_addr);
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return val;
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}
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static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
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{
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return cvmx_read_csr((__force uint64_t) csr_addr);
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}
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static inline void cvmx_send_single(uint64_t data)
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{
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const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
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cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
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}
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static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
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{
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union {
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uint64_t u64;
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struct {
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uint64_t scraddr:8;
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uint64_t len:8;
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uint64_t addr:48;
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} s;
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} addr;
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addr.u64 = csr_addr;
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addr.s.scraddr = scraddr >> 3;
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addr.s.len = 1;
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cvmx_send_single(addr.u64);
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}
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/* Return true if Octeon is CN38XX pass 1 */
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static inline int cvmx_octeon_is_pass1(void)
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{
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#if OCTEON_IS_COMMON_BINARY()
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return 0; /* Pass 1 isn't supported for common binaries */
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#else
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/* Now that we know we're built for a specific model, only check CN38XX */
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#if OCTEON_IS_MODEL(OCTEON_CN38XX)
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return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
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#else
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return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
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#endif
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#endif
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}
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static inline unsigned int cvmx_get_core_num(void)
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{
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unsigned int core_num;
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CVMX_RDHWRNV(core_num, 0);
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return core_num;
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}
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|
||
|
|
/* Maximum # of bits to define core in node */
|
||
|
|
#define CVMX_NODE_NO_SHIFT 7
|
||
|
|
#define CVMX_NODE_MASK 0x3
|
||
|
|
static inline unsigned int cvmx_get_node_num(void)
|
||
|
|
{
|
||
|
|
unsigned int core_num = cvmx_get_core_num();
|
||
|
|
|
||
|
|
return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int cvmx_get_local_core_num(void)
|
||
|
|
{
|
||
|
|
return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define CVMX_NODE_BITS (2) /* Number of bits to define a node */
|
||
|
|
#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
|
||
|
|
#define CVMX_NODE_IO_SHIFT (36)
|
||
|
|
#define CVMX_NODE_MEM_SHIFT (40)
|
||
|
|
#define CVMX_NODE_IO_MASK ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
|
||
|
|
|
||
|
|
static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
|
||
|
|
uint64_t val)
|
||
|
|
{
|
||
|
|
uint64_t composite_csr_addr, node_addr;
|
||
|
|
|
||
|
|
node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
|
||
|
|
composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
|
||
|
|
|
||
|
|
cvmx_write64_uint64(composite_csr_addr, val);
|
||
|
|
if (((csr_addr >> 40) & 0x7ffff) == (0x118))
|
||
|
|
cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
|
||
|
|
{
|
||
|
|
uint64_t node_addr;
|
||
|
|
|
||
|
|
node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
|
||
|
|
(node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
|
||
|
|
return cvmx_read_csr(node_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Returns the number of bits set in the provided value.
|
||
|
|
* Simple wrapper for POP instruction.
|
||
|
|
*
|
||
|
|
* @val: 32 bit value to count set bits in
|
||
|
|
*
|
||
|
|
* Returns Number of bits set
|
||
|
|
*/
|
||
|
|
static inline uint32_t cvmx_pop(uint32_t val)
|
||
|
|
{
|
||
|
|
uint32_t pop;
|
||
|
|
CVMX_POP(pop, val);
|
||
|
|
return pop;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Returns the number of bits set in the provided value.
|
||
|
|
* Simple wrapper for DPOP instruction.
|
||
|
|
*
|
||
|
|
* @val: 64 bit value to count set bits in
|
||
|
|
*
|
||
|
|
* Returns Number of bits set
|
||
|
|
*/
|
||
|
|
static inline int cvmx_dpop(uint64_t val)
|
||
|
|
{
|
||
|
|
int pop;
|
||
|
|
CVMX_DPOP(pop, val);
|
||
|
|
return pop;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Provide current cycle counter as a return value
|
||
|
|
*
|
||
|
|
* Returns current cycle counter
|
||
|
|
*/
|
||
|
|
|
||
|
|
static inline uint64_t cvmx_get_cycle(void)
|
||
|
|
{
|
||
|
|
uint64_t cycle;
|
||
|
|
CVMX_RDHWR(cycle, 31);
|
||
|
|
return cycle;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Reads a chip global cycle counter. This counts CPU cycles since
|
||
|
|
* chip reset. The counter is 64 bit.
|
||
|
|
* This register does not exist on CN38XX pass 1 silicion
|
||
|
|
*
|
||
|
|
* Returns Global chip cycle count since chip reset.
|
||
|
|
*/
|
||
|
|
static inline uint64_t cvmx_get_cycle_global(void)
|
||
|
|
{
|
||
|
|
if (cvmx_octeon_is_pass1())
|
||
|
|
return 0;
|
||
|
|
else
|
||
|
|
return cvmx_read64(CVMX_IPD_CLK_COUNT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This macro spins on a field waiting for it to reach a value. It
|
||
|
|
* is common in code to need to wait for a specific field in a CSR
|
||
|
|
* to match a specific value. Conceptually this macro expands to:
|
||
|
|
*
|
||
|
|
* 1) read csr at "address" with a csr typedef of "type"
|
||
|
|
* 2) Check if ("type".s."field" "op" "value")
|
||
|
|
* 3) If #2 isn't true loop to #1 unless too much time has passed.
|
||
|
|
*/
|
||
|
|
#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
|
||
|
|
( \
|
||
|
|
{ \
|
||
|
|
int result; \
|
||
|
|
do { \
|
||
|
|
uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
|
||
|
|
cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
|
||
|
|
type c; \
|
||
|
|
while (1) { \
|
||
|
|
c.u64 = cvmx_read_csr(address); \
|
||
|
|
if ((c.s.field) op(value)) { \
|
||
|
|
result = 0; \
|
||
|
|
break; \
|
||
|
|
} else if (cvmx_get_cycle() > done) { \
|
||
|
|
result = -1; \
|
||
|
|
break; \
|
||
|
|
} else \
|
||
|
|
__delay(100); \
|
||
|
|
} \
|
||
|
|
} while (0); \
|
||
|
|
result; \
|
||
|
|
})
|
||
|
|
|
||
|
|
/***************************************************************************/
|
||
|
|
|
||
|
|
/* Return the number of cores available in the chip */
|
||
|
|
static inline uint32_t cvmx_octeon_num_cores(void)
|
||
|
|
{
|
||
|
|
u64 ciu_fuse_reg;
|
||
|
|
u64 ciu_fuse;
|
||
|
|
|
||
|
|
if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
|
||
|
|
ciu_fuse_reg = CVMX_CIU3_FUSE;
|
||
|
|
else
|
||
|
|
ciu_fuse_reg = CVMX_CIU_FUSE;
|
||
|
|
ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
|
||
|
|
return cvmx_dpop(ciu_fuse);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __CVMX_H__ */
|