319 lines
11 KiB
C
319 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin <wuzhangjin@gmail.com>
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*/
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#ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H
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#define __ASM_MACH_LOONGSON2EF_LOONGSON_H
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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/* loongson internal northbridge initialization */
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extern void bonito_irq_init(void);
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/* machine-specific reboot/halt operation */
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extern void mach_prepare_reboot(void);
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extern void mach_prepare_shutdown(void);
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/* environment arguments from bootloader */
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extern u32 cpu_clock_freq;
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extern u32 memsize, highmemsize;
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/* loongson-specific command line, env and memory initialization */
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extern void __init prom_init_memory(void);
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extern void __init prom_init_machtype(void);
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extern void __init prom_init_env(void);
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#ifdef CONFIG_LOONGSON_UART_BASE
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extern unsigned long _loongson_uart_base, loongson_uart_base;
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extern void prom_init_loongson_uart_base(void);
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#endif
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static inline void prom_init_uart_base(void)
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{
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#ifdef CONFIG_LOONGSON_UART_BASE
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prom_init_loongson_uart_base();
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#endif
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}
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/* irq operation functions */
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extern void bonito_irqdispatch(void);
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extern void __init bonito_irq_init(void);
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extern void __init mach_init_irq(void);
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extern void mach_irq_dispatch(unsigned int pending);
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extern int mach_i8259_irq(void);
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/* We need this in some places... */
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#define delay() ({ \
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int x; \
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for (x = 0; x < 100000; x++) \
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__asm__ __volatile__(""); \
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})
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#define LOONGSON_REG(x) \
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(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
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#define LOONGSON_IRQ_BASE 32
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#define LOONGSON_FLASH_BASE 0x1c000000
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#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
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#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
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#define LOONGSON_LIO0_BASE 0x1e000000
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#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
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#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
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#define LOONGSON_BOOT_BASE 0x1fc00000
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#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
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#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
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#define LOONGSON_REG_BASE 0x1fe00000
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#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
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#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
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#define LOONGSON_LIO1_BASE 0x1ff00000
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#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
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#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
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#define LOONGSON_PCILO0_BASE 0x10000000
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#define LOONGSON_PCILO1_BASE 0x14000000
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#define LOONGSON_PCILO2_BASE 0x18000000
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#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
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#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
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#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
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#define LOONGSON_PCICFG_BASE 0x1fe80000
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#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
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#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
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#define LOONGSON_PCIIO_BASE 0x1fd00000
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#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
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#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
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/* Loongson Register Bases */
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#define LOONGSON_PCICONFIGBASE 0x00
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#define LOONGSON_REGBASE 0x100
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/* PCI Configuration Registers */
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#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
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#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
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#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
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#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
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#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
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#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
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#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
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#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
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#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
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#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
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#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
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#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
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#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
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#define LOONGSON_PCICMD_PERR_CLR 0x80000000
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#define LOONGSON_PCICMD_SERR_CLR 0x40000000
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#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
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#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
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#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
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#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
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#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
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#define LOONGSON_PCICMD_ASTEPEN 0x00000080
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#define LOONGSON_PCICMD_SERREN 0x00000100
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#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
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#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
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/* Loongson h/w Configuration */
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#define LOONGSON_GENCFG_OFFSET 0x4
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#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
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#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
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#define LOONGSON_GENCFG_SNOOPEN 0x00000002
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#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
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#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
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#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
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#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
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#define LOONGSON_GENCFG_BYTESWAP 0x00000040
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#define LOONGSON_GENCFG_UNCACHED 0x00000080
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#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
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#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
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#define LOONGSON_GENCFG_CACHEALG 0x00000c00
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#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
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#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
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#define LOONGSON_GENCFG_CACHESTOP 0x00002000
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#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
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#define LOONGSON_GENCFG_BUSERREN 0x00008000
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#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
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#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
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/* PCI address map control */
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#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
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#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
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#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
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/* GPIO Regs - r/w */
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#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
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#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
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/* ICU Configuration Regs - r/w */
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#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
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#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
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#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
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/* ICU Enable Regs - IntEn & IntISR are r/o. */
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#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
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#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
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#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
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#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
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/* ICU */
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#define LOONGSON_ICU_MBOXES 0x0000000f
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#define LOONGSON_ICU_MBOXES_SHIFT 0
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#define LOONGSON_ICU_DMARDY 0x00000010
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#define LOONGSON_ICU_DMAEMPTY 0x00000020
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#define LOONGSON_ICU_COPYRDY 0x00000040
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#define LOONGSON_ICU_COPYEMPTY 0x00000080
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#define LOONGSON_ICU_COPYERR 0x00000100
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#define LOONGSON_ICU_PCIIRQ 0x00000200
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#define LOONGSON_ICU_MASTERERR 0x00000400
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#define LOONGSON_ICU_SYSTEMERR 0x00000800
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#define LOONGSON_ICU_DRAMPERR 0x00001000
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#define LOONGSON_ICU_RETRYERR 0x00002000
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#define LOONGSON_ICU_GPIOS 0x01ff0000
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#define LOONGSON_ICU_GPIOS_SHIFT 16
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#define LOONGSON_ICU_GPINS 0x7e000000
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#define LOONGSON_ICU_GPINS_SHIFT 25
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#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
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#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
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#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
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/* PCI prefetch window base & mask */
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#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
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#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
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#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
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#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
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/* PCI_Hit*_Sel_* */
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#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
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#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
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#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
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#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
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#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
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#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
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/* PXArb Config & Status */
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#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
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#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
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/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
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#define LOONGSON_CHIPCFG (void __iomem *)TO_UNCAC(0x1fc00180)
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/* pcimap */
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#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
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#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
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#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
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#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
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#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
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#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
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#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
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#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
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((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
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#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
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#include <linux/cpufreq.h>
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extern struct cpufreq_frequency_table loongson2_clockmod_table[];
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extern int loongson2_cpu_set_rate(unsigned long rate_khz);
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#endif
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/*
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* address windows configuration module
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*
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* loongson2e do not have this module
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*/
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#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
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/* address window config module base address */
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#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
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#define LOONGSON_ADDRWINCFG_SIZE 0x180
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extern unsigned long _loongson_addrwincfg_base;
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#define LOONGSON_ADDRWINCFG(offset) \
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(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
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#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
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#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
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#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
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#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
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#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
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#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
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#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
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#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
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#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
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#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
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#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
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#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
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#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
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#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
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#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
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#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
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#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
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#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
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#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
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#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
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#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
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#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
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#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
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#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
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#define ADDRWIN_WIN0 0
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#define ADDRWIN_WIN1 1
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#define ADDRWIN_WIN2 2
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#define ADDRWIN_WIN3 3
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#define ADDRWIN_MAP_DST_DDR 0
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#define ADDRWIN_MAP_DST_PCI 1
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#define ADDRWIN_MAP_DST_LIO 1
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/*
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* s: CPU, PCIDMA
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* d: DDR, PCI, LIO
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* win: 0, 1, 2, 3
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* src: map source
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* dst: map destination
|
||
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* size: ~mask + 1
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||
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*/
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||
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#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
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s##_WIN##w##_BASE = (src); \
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||
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|
s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
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||
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|
s##_WIN##w##_MASK = ~(size-1); \
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||
|
|
} while (0)
|
||
|
|
|
||
|
|
#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
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||
|
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LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
|
||
|
|
#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
|
||
|
|
LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
|
||
|
|
#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
|
||
|
|
LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
|
||
|
|
|
||
|
|
#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
|
||
|
|
|
||
|
|
#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
|