270 lines
8.1 KiB
C
270 lines
8.1 KiB
C
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* But use these as seldom as possible since they are much more slower
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* than regular operations.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/irqflags.h>
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#include <linux/types.h>
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#include <asm/asm.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cmpxchg.h>
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#include <asm/sync.h>
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#define ATOMIC_OPS(pfx, type) \
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static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
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{ \
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return READ_ONCE(v->counter); \
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} \
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\
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static __always_inline void arch_##pfx##_set(pfx##_t *v, type i) \
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{ \
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WRITE_ONCE(v->counter, i); \
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} \
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\
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static __always_inline type \
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arch_##pfx##_cmpxchg(pfx##_t *v, type o, type n) \
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{ \
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return arch_cmpxchg(&v->counter, o, n); \
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} \
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\
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static __always_inline type arch_##pfx##_xchg(pfx##_t *v, type n) \
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{ \
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return arch_xchg(&v->counter, n); \
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}
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ATOMIC_OPS(atomic, int)
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#ifdef CONFIG_64BIT
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# define ATOMIC64_INIT(i) { (i) }
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ATOMIC_OPS(atomic64, s64)
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#endif
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#define ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
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{ \
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type temp; \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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return; \
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} \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" " #sc " %0, %1 \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" .set pop \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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}
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#define ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ type \
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arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
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{ \
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type temp, result; \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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return result; \
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} \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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static __inline__ type \
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arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
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{ \
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int temp, result; \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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return result; \
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} \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" .set pop \n" \
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" move %0, %1 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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\
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return result; \
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}
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
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ATOMIC_OPS(atomic, add, int, +=, addu, ll, sc)
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ATOMIC_OPS(atomic, sub, int, -=, subu, ll, sc)
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#ifdef CONFIG_64BIT
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ATOMIC_OPS(atomic64, add, s64, +=, daddu, lld, scd)
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ATOMIC_OPS(atomic64, sub, s64, -=, dsubu, lld, scd)
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# define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
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# define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
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# define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
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# define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
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#endif /* CONFIG_64BIT */
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
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ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
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ATOMIC_OPS(atomic, and, int, &=, and, ll, sc)
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ATOMIC_OPS(atomic, or, int, |=, or, ll, sc)
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ATOMIC_OPS(atomic, xor, int, ^=, xor, ll, sc)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#ifdef CONFIG_64BIT
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ATOMIC_OPS(atomic64, and, s64, &=, and, lld, scd)
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ATOMIC_OPS(atomic64, or, s64, |=, or, lld, scd)
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ATOMIC_OPS(atomic64, xor, s64, ^=, xor, lld, scd)
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# define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
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# define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
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# define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
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#endif
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/*
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* atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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#define ATOMIC_SIP_OP(pfx, type, op, ll, sc) \
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static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
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{ \
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type temp, result; \
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\
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smp_mb__before_atomic(); \
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\
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if (!kernel_uses_llsc) { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result -= i; \
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if (result >= 0) \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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smp_mb__after_atomic(); \
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return result; \
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} \
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\
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__asm__ __volatile__( \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " #ll " %1, %2 # atomic_sub_if_positive\n" \
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" .set pop \n" \
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" " #op " %0, %1, %3 \n" \
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" move %1, %0 \n" \
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" bltz %0, 2f \n" \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " #sc " %1, %2 \n" \
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" " __stringify(SC_BEQZ) " %1, 1b \n" \
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"2: " __SYNC(full, loongson3_war) " \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) \
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: __LLSC_CLOBBER); \
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\
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/* \
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* In the Loongson3 workaround case we already have a \
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* completion barrier at 2: above, which is needed due to the \
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* bltz that can branch to code outside of the LL/SC loop. As \
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* such, we don't need to emit another barrier here. \
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*/ \
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if (__SYNC_loongson3_war == 0) \
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smp_mb__after_atomic(); \
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\
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return result; \
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}
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ATOMIC_SIP_OP(atomic, int, subu, ll, sc)
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#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
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#ifdef CONFIG_64BIT
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ATOMIC_SIP_OP(atomic64, s64, dsubu, lld, scd)
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#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
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#endif
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#undef ATOMIC_SIP_OP
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#endif /* _ASM_ATOMIC_H */
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