103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/mm/flush.c
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*
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* Copyright (C) 1995-2002 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/cache.h>
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#include <asm/tlbflush.h>
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void sync_icache_aliases(unsigned long start, unsigned long end)
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{
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if (icache_is_aliasing()) {
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dcache_clean_pou(start, end);
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icache_inval_all_pou();
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} else {
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/*
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* Don't issue kick_all_cpus_sync() after I-cache invalidation
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* for user mappings.
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*/
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caches_clean_inval_pou(start, end);
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}
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}
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static void flush_ptrace_access(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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if (vma->vm_flags & VM_EXEC)
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sync_icache_aliases(start, end);
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}
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/*
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* Copy user data from/to a page which is mapped into a different processes
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* address space. Really, we want to allow our "user space" model to handle
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* this.
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*/
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *dst, const void *src,
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unsigned long len)
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{
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memcpy(dst, src, len);
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flush_ptrace_access(vma, (unsigned long)dst, (unsigned long)dst + len);
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}
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void __sync_icache_dcache(pte_t pte)
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{
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struct page *page = pte_page(pte);
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/*
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* HugeTLB pages are always fully mapped, so only setting head page's
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* PG_dcache_clean flag is enough.
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*/
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if (PageHuge(page))
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page = compound_head(page);
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if (!test_bit(PG_dcache_clean, &page->flags)) {
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sync_icache_aliases((unsigned long)page_address(page),
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(unsigned long)page_address(page) +
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page_size(page));
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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EXPORT_SYMBOL_GPL(__sync_icache_dcache);
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/*
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* This function is called when a page has been modified by the kernel. Mark
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* it as dirty for later flushing when mapped in user space (if executable,
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* see __sync_icache_dcache).
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*/
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void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/*
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* Additional functions defined in assembly.
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*/
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EXPORT_SYMBOL(caches_clean_inval_pou);
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#ifdef CONFIG_ARCH_HAS_PMEM_API
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void arch_wb_cache_pmem(void *addr, size_t size)
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{
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/* Ensure order against any prior non-cacheable writes */
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dmb(osh);
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dcache_clean_pop((unsigned long)addr, (unsigned long)addr + size);
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}
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EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
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void arch_invalidate_pmem(void *addr, size_t size)
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{
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dcache_inval_poc((unsigned long)addr, (unsigned long)addr + size);
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}
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EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
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#endif
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