487 lines
13 KiB
C
487 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_mmu.h>
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#include "vgic.h"
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static inline void vgic_v2_write_lr(int lr, u32 val)
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{
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void __iomem *base = kvm_vgic_global_state.vctrl_base;
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writel_relaxed(val, base + GICH_LR0 + (lr * 4));
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}
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void vgic_v2_init_lrs(void)
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{
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int i;
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for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
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vgic_v2_write_lr(i, 0);
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}
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
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{
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struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
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cpuif->vgic_hcr |= GICH_HCR_UIE;
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}
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static bool lr_signals_eoi_mi(u32 lr_val)
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{
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return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
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!(lr_val & GICH_LR_HW);
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}
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/*
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* transfer the content of the LRs back into the corresponding ap_list:
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* - active bit is transferred as is
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* - pending bit is
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* - transferred as is in case of edge sensitive IRQs
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* - set to the line-level (resample time) for level sensitive IRQs
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*/
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
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int lr;
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DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
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cpuif->vgic_hcr &= ~GICH_HCR_UIE;
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for (lr = 0; lr < vgic_cpu->vgic_v2.used_lrs; lr++) {
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u32 val = cpuif->vgic_lr[lr];
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u32 cpuid, intid = val & GICH_LR_VIRTUALID;
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struct vgic_irq *irq;
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bool deactivated;
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/* Extract the source vCPU id from the LR */
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cpuid = val & GICH_LR_PHYSID_CPUID;
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cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
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cpuid &= 7;
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/* Notify fds when the guest EOI'ed a level-triggered SPI */
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if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
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kvm_notify_acked_irq(vcpu->kvm, 0,
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intid - VGIC_NR_PRIVATE_IRQS);
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irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
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raw_spin_lock(&irq->irq_lock);
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/* Always preserve the active bit, note deactivation */
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deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT);
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irq->active = !!(val & GICH_LR_ACTIVE_BIT);
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if (irq->active && vgic_irq_is_sgi(intid))
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irq->active_source = cpuid;
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/* Edge is the only case where we preserve the pending bit */
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if (irq->config == VGIC_CONFIG_EDGE &&
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(val & GICH_LR_PENDING_BIT)) {
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irq->pending_latch = true;
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if (vgic_irq_is_sgi(intid))
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irq->source |= (1 << cpuid);
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}
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/*
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* Clear soft pending state when level irqs have been acked.
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*/
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if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
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irq->pending_latch = false;
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/* Handle resampling for mapped interrupts if required */
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vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT);
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raw_spin_unlock(&irq->irq_lock);
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vgic_put_irq(vcpu->kvm, irq);
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}
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cpuif->used_lrs = 0;
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}
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/*
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* Populates the particular LR with the state of a given IRQ:
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* - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
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* - for a level sensitive IRQ the pending state value is unchanged;
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* it is dictated directly by the input level
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*
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* If @irq describes an SGI with multiple sources, we choose the
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* lowest-numbered source VCPU and clear that bit in the source bitmap.
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*
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* The irq_lock must be held by the caller.
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*/
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
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{
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u32 val = irq->intid;
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bool allow_pending = true;
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if (irq->active) {
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val |= GICH_LR_ACTIVE_BIT;
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if (vgic_irq_is_sgi(irq->intid))
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val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
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if (vgic_irq_is_multi_sgi(irq)) {
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allow_pending = false;
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val |= GICH_LR_EOI;
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}
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}
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if (irq->group)
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val |= GICH_LR_GROUP1;
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if (irq->hw && !vgic_irq_needs_resampling(irq)) {
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val |= GICH_LR_HW;
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val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
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/*
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* Never set pending+active on a HW interrupt, as the
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* pending state is kept at the physical distributor
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* level.
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*/
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if (irq->active)
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allow_pending = false;
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} else {
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if (irq->config == VGIC_CONFIG_LEVEL) {
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val |= GICH_LR_EOI;
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/*
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* Software resampling doesn't work very well
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* if we allow P+A, so let's not do that.
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*/
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if (irq->active)
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allow_pending = false;
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}
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}
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if (allow_pending && irq_is_pending(irq)) {
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val |= GICH_LR_PENDING_BIT;
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if (irq->config == VGIC_CONFIG_EDGE)
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irq->pending_latch = false;
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if (vgic_irq_is_sgi(irq->intid)) {
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u32 src = ffs(irq->source);
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if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
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irq->intid))
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return;
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val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
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irq->source &= ~(1 << (src - 1));
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if (irq->source) {
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irq->pending_latch = true;
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val |= GICH_LR_EOI;
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}
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}
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}
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/*
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* Level-triggered mapped IRQs are special because we only observe
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* rising edges as input to the VGIC. We therefore lower the line
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* level here, so that we can take new virtual IRQs. See
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* vgic_v2_fold_lr_state for more info.
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*/
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if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
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irq->line_level = false;
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/* The GICv2 LR only holds five bits of priority. */
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val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
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}
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
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{
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
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}
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void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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u32 vmcr;
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vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
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GICH_VMCR_ENABLE_GRP0_MASK;
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vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
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GICH_VMCR_ENABLE_GRP1_MASK;
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vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
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GICH_VMCR_ACK_CTL_MASK;
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vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
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GICH_VMCR_FIQ_EN_MASK;
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vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
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GICH_VMCR_CBPR_MASK;
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vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
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GICH_VMCR_EOI_MODE_MASK;
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vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
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GICH_VMCR_ALIAS_BINPOINT_MASK;
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vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
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GICH_VMCR_BINPOINT_MASK;
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vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
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GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
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cpu_if->vgic_vmcr = vmcr;
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}
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void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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u32 vmcr;
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vmcr = cpu_if->vgic_vmcr;
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vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
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GICH_VMCR_ENABLE_GRP0_SHIFT;
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vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
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GICH_VMCR_ENABLE_GRP1_SHIFT;
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vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
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GICH_VMCR_ACK_CTL_SHIFT;
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vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
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GICH_VMCR_FIQ_EN_SHIFT;
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vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
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GICH_VMCR_CBPR_SHIFT;
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vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
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GICH_VMCR_EOI_MODE_SHIFT;
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vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
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GICH_VMCR_ALIAS_BINPOINT_SHIFT;
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vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
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GICH_VMCR_BINPOINT_SHIFT;
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vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
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GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
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}
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void vgic_v2_enable(struct kvm_vcpu *vcpu)
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{
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/*
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* By forcing VMCR to zero, the GIC will restore the binary
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* points to their reset values. Anything else resets to zero
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* anyway.
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*/
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vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
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/* Get the show on the road... */
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vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
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}
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/* check for overlapping regions and for regions crossing the end of memory */
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static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
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{
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if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
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return false;
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if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
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return false;
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if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
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return true;
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if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
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return true;
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return false;
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}
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int vgic_v2_map_resources(struct kvm *kvm)
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{
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struct vgic_dist *dist = &kvm->arch.vgic;
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int ret = 0;
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if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
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IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
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kvm_debug("Need to set vgic cpu and dist addresses first\n");
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return -ENXIO;
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}
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if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
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kvm_debug("VGIC CPU and dist frames overlap\n");
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return -EINVAL;
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}
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/*
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* Initialize the vgic if this hasn't already been done on demand by
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* accessing the vgic state from userspace.
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*/
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ret = vgic_init(kvm);
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if (ret) {
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kvm_err("Unable to initialize VGIC dynamic data structures\n");
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return ret;
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}
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ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
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if (ret) {
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kvm_err("Unable to register VGIC MMIO regions\n");
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return ret;
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}
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if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
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ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
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kvm_vgic_global_state.vcpu_base,
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KVM_VGIC_V2_CPU_SIZE, true);
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if (ret) {
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kvm_err("Unable to remap VGIC CPU to VCPU\n");
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return ret;
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}
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}
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return 0;
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}
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DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
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/**
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* vgic_v2_probe - probe for a VGICv2 compatible interrupt controller
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* @info: pointer to the GIC description
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*
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* Returns 0 if the VGICv2 has been probed successfully, returns an error code
|
||
|
|
* otherwise
|
||
|
|
*/
|
||
|
|
int vgic_v2_probe(const struct gic_kvm_info *info)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
u32 vtr;
|
||
|
|
|
||
|
|
if (is_protected_kvm_enabled()) {
|
||
|
|
kvm_err("GICv2 not supported in protected mode\n");
|
||
|
|
return -ENXIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!info->vctrl.start) {
|
||
|
|
kvm_err("GICH not present in the firmware table\n");
|
||
|
|
return -ENXIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!PAGE_ALIGNED(info->vcpu.start) ||
|
||
|
|
!PAGE_ALIGNED(resource_size(&info->vcpu))) {
|
||
|
|
kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
|
||
|
|
|
||
|
|
ret = create_hyp_io_mappings(info->vcpu.start,
|
||
|
|
resource_size(&info->vcpu),
|
||
|
|
&kvm_vgic_global_state.vcpu_base_va,
|
||
|
|
&kvm_vgic_global_state.vcpu_hyp_va);
|
||
|
|
if (ret) {
|
||
|
|
kvm_err("Cannot map GICV into hyp\n");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
static_branch_enable(&vgic_v2_cpuif_trap);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = create_hyp_io_mappings(info->vctrl.start,
|
||
|
|
resource_size(&info->vctrl),
|
||
|
|
&kvm_vgic_global_state.vctrl_base,
|
||
|
|
&kvm_vgic_global_state.vctrl_hyp);
|
||
|
|
if (ret) {
|
||
|
|
kvm_err("Cannot map VCTRL into hyp\n");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
|
||
|
|
kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
|
||
|
|
|
||
|
|
ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
|
||
|
|
if (ret) {
|
||
|
|
kvm_err("Cannot register GICv2 KVM device\n");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
kvm_vgic_global_state.can_emulate_gicv2 = true;
|
||
|
|
kvm_vgic_global_state.vcpu_base = info->vcpu.start;
|
||
|
|
kvm_vgic_global_state.type = VGIC_V2;
|
||
|
|
kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
|
||
|
|
|
||
|
|
kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
out:
|
||
|
|
if (kvm_vgic_global_state.vctrl_base)
|
||
|
|
iounmap(kvm_vgic_global_state.vctrl_base);
|
||
|
|
if (kvm_vgic_global_state.vcpu_base_va)
|
||
|
|
iounmap(kvm_vgic_global_state.vcpu_base_va);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
|
||
|
|
{
|
||
|
|
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
|
||
|
|
u64 used_lrs = cpu_if->used_lrs;
|
||
|
|
u64 elrsr;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
elrsr = readl_relaxed(base + GICH_ELRSR0);
|
||
|
|
if (unlikely(used_lrs > 32))
|
||
|
|
elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
|
||
|
|
|
||
|
|
for (i = 0; i < used_lrs; i++) {
|
||
|
|
if (elrsr & (1UL << i))
|
||
|
|
cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
|
||
|
|
else
|
||
|
|
cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
|
||
|
|
|
||
|
|
writel_relaxed(0, base + GICH_LR0 + (i * 4));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void vgic_v2_save_state(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
void __iomem *base = kvm_vgic_global_state.vctrl_base;
|
||
|
|
u64 used_lrs = vcpu->arch.vgic_cpu.vgic_v2.used_lrs;
|
||
|
|
|
||
|
|
if (!base)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (used_lrs) {
|
||
|
|
save_lrs(vcpu, base);
|
||
|
|
writel_relaxed(0, base + GICH_HCR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
|
||
|
|
void __iomem *base = kvm_vgic_global_state.vctrl_base;
|
||
|
|
u64 used_lrs = cpu_if->used_lrs;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (!base)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (used_lrs) {
|
||
|
|
writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
|
||
|
|
for (i = 0; i < used_lrs; i++) {
|
||
|
|
writel_relaxed(cpu_if->vgic_lr[i],
|
||
|
|
base + GICH_LR0 + (i * 4));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void vgic_v2_load(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
|
||
|
|
|
||
|
|
writel_relaxed(cpu_if->vgic_vmcr,
|
||
|
|
kvm_vgic_global_state.vctrl_base + GICH_VMCR);
|
||
|
|
writel_relaxed(cpu_if->vgic_apr,
|
||
|
|
kvm_vgic_global_state.vctrl_base + GICH_APR);
|
||
|
|
}
|
||
|
|
|
||
|
|
void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
|
||
|
|
|
||
|
|
cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
|
||
|
|
}
|
||
|
|
|
||
|
|
void vgic_v2_put(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
|
||
|
|
|
||
|
|
vgic_v2_vmcr_sync(vcpu);
|
||
|
|
cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
|
||
|
|
}
|