297 lines
9.9 KiB
C
297 lines
9.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_PGTABLE_HWDEF_H
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#define __ASM_PGTABLE_HWDEF_H
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#include <asm/memory.h>
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/*
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* Number of page-table levels required to address 'va_bits' wide
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* address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
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* bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
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*
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* levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
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*
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* where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
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*
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* We cannot include linux/kernel.h which defines DIV_ROUND_UP here
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* due to build issues. So we open code DIV_ROUND_UP here:
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*
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* ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
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*
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* which gets simplified as :
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*/
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#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
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/*
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* Size mapped by an entry at level n ( 0 <= n <= 3)
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* We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
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* in the final page. The maximum number of translation levels supported by
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* the architecture is 4. Hence, starting at level n, we have further
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* ((4 - n) - 1) levels of translation excluding the offset within the page.
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* So, the total number of bits mapped by an entry at level n is :
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*
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* ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
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*
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* Rearranging it a bit we get :
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* (4 - n) * (PAGE_SHIFT - 3) + 3
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*/
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#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
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#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
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/*
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* PMD_SHIFT determines the size a level 2 page table entry can map.
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*/
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
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#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PTRS_PER_PMD PTRS_PER_PTE
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#endif
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/*
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* PUD_SHIFT determines the size a level 1 page table entry can map.
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*/
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
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#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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#define PTRS_PER_PUD PTRS_PER_PTE
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#endif
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map
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* (depending on the configuration, this level can be 0, 1 or 2).
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*/
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#define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
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/*
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* Contiguous page definitions.
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*/
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#define CONT_PTE_SHIFT (CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
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#define CONT_PTES (1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
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#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
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#define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1))
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#define CONT_PMD_SHIFT (CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
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#define CONT_PMDS (1 << (CONT_PMD_SHIFT - PMD_SHIFT))
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#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
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#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
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/*
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* Hardware page table definitions.
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*
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* Level 0 descriptor (P4D).
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*/
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#define P4D_TYPE_TABLE (_AT(p4dval_t, 3) << 0)
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#define P4D_TABLE_BIT (_AT(p4dval_t, 1) << 1)
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#define P4D_TYPE_MASK (_AT(p4dval_t, 3) << 0)
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#define P4D_TYPE_SECT (_AT(p4dval_t, 1) << 0)
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#define P4D_SECT_RDONLY (_AT(p4dval_t, 1) << 7) /* AP[2] */
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#define P4D_TABLE_PXN (_AT(p4dval_t, 1) << 59)
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#define P4D_TABLE_UXN (_AT(p4dval_t, 1) << 60)
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/*
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* Level 1 descriptor (PUD).
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*/
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#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
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#define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1)
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#define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0)
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#define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0)
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#define PUD_SECT_RDONLY (_AT(pudval_t, 1) << 7) /* AP[2] */
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#define PUD_TABLE_PXN (_AT(pudval_t, 1) << 59)
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#define PUD_TABLE_UXN (_AT(pudval_t, 1) << 60)
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/*
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* Level 2 descriptor (PMD).
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*/
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#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
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#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
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/*
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* Section
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*/
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#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
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#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
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#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
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#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
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#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
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#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
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#define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52)
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#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
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#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
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#define PMD_TABLE_PXN (_AT(pmdval_t, 1) << 59)
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#define PMD_TABLE_UXN (_AT(pmdval_t, 1) << 60)
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
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#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
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/*
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* Level 3 descriptor (PTE).
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*/
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#define PTE_VALID (_AT(pteval_t, 1) << 0)
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#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
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#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
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#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
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#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
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#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
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#define PTE_GP (_AT(pteval_t, 1) << 50) /* BTI guarded */
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#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */
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#define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */
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#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
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#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
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#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
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#ifdef CONFIG_ARM64_PA_BITS_52
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#define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12)
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#define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH)
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#else
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#define PTE_ADDR_MASK PTE_ADDR_LOW
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#endif
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
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#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
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/*
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* Memory Attribute override for Stage-2 (MemAttr[3:0])
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*/
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#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
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/*
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* Highest possible physical address supported.
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*/
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#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
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#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
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#define TTBR_CNP_BIT (UL(1) << 0)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ_OFFSET 0
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#define TCR_T1SZ_OFFSET 16
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#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
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#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
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#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
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#define TCR_TxSZ_WIDTH 6
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#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
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#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
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#define TCR_EPD0_SHIFT 7
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#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
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#define TCR_IRGN0_SHIFT 8
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#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
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#define TCR_EPD1_SHIFT 23
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#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
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#define TCR_IRGN1_SHIFT 24
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#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
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#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
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#define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
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#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
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#define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
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#define TCR_ORGN0_SHIFT 10
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#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN1_SHIFT 26
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#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
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#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
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#define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
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#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
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#define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
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#define TCR_SH0_SHIFT 12
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#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
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#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
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#define TCR_SH1_SHIFT 28
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#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
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#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
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#define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
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#define TCR_TG0_SHIFT 14
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#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
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#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
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#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
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#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
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#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
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#define TCR_IPS_SHIFT 32
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#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
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#define TCR_A1 (UL(1) << 22)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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#define TCR_TBI1 (UL(1) << 38)
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#define TCR_HA (UL(1) << 39)
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#define TCR_HD (UL(1) << 40)
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#define TCR_TBID1 (UL(1) << 52)
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#define TCR_NFD0 (UL(1) << 53)
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#define TCR_NFD1 (UL(1) << 54)
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#define TCR_E0PD0 (UL(1) << 55)
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#define TCR_E0PD1 (UL(1) << 56)
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#define TCR_TCMA0 (UL(1) << 57)
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#define TCR_TCMA1 (UL(1) << 58)
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/*
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* TTBR.
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*/
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#ifdef CONFIG_ARM64_PA_BITS_52
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/*
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* This should be GENMASK_ULL(47, 2).
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* TTBR_ELx[1] is RES0 in this configuration.
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*/
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#define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)
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#endif
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#ifdef CONFIG_ARM64_VA_BITS_52
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/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
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#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
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||
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(UL(1) << (48 - PGDIR_SHIFT))) * 8)
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||
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#endif
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||
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|
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||
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#endif
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