361 lines
10 KiB
C
361 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Kernel Probes Jump Optimization (Optprobes)
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*
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* Copyright (C) IBM Corporation, 2002, 2004
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* Copyright (C) Hitachi Ltd., 2012
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* Copyright (C) Huawei Inc., 2014
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*/
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#include <linux/kprobes.h>
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#include <linux/jump_label.h>
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#include <asm/kprobes.h>
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#include <asm/cacheflush.h>
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/* for arm_gen_branch */
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#include <asm/insn.h>
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/* for patch_text */
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#include <asm/patch.h>
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#include "core.h"
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/*
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* See register_usage_flags. If the probed instruction doesn't use PC,
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* we can copy it into template and have it executed directly without
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* simulation or emulation.
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*/
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#define ARM_REG_PC 15
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#define can_kprobe_direct_exec(m) (!test_bit(ARM_REG_PC, &(m)))
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/*
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* NOTE: the first sub and add instruction will be modified according
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* to the stack cost of the instruction.
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*/
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asm (
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".global optprobe_template_entry\n"
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"optprobe_template_entry:\n"
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".global optprobe_template_sub_sp\n"
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"optprobe_template_sub_sp:"
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" sub sp, sp, #0xff\n"
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" stmia sp, {r0 - r14} \n"
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".global optprobe_template_add_sp\n"
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"optprobe_template_add_sp:"
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" add r3, sp, #0xff\n"
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" str r3, [sp, #52]\n"
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" mrs r4, cpsr\n"
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" str r4, [sp, #64]\n"
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" mov r1, sp\n"
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" ldr r0, 1f\n"
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" ldr r2, 2f\n"
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/*
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* AEABI requires an 8-bytes alignment stack. If
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* SP % 8 != 0 (SP % 4 == 0 should be ensured),
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* alloc more bytes here.
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*/
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" and r4, sp, #4\n"
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" sub sp, sp, r4\n"
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#if __LINUX_ARM_ARCH__ >= 5
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" blx r2\n"
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#else
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" mov lr, pc\n"
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" mov pc, r2\n"
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#endif
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" add sp, sp, r4\n"
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" ldr r1, [sp, #64]\n"
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" tst r1, #"__stringify(PSR_T_BIT)"\n"
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" ldrne r2, [sp, #60]\n"
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" orrne r2, #1\n"
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" strne r2, [sp, #60] @ set bit0 of PC for thumb\n"
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" msr cpsr_cxsf, r1\n"
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".global optprobe_template_restore_begin\n"
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"optprobe_template_restore_begin:\n"
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" ldmia sp, {r0 - r15}\n"
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".global optprobe_template_restore_orig_insn\n"
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"optprobe_template_restore_orig_insn:\n"
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" nop\n"
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".global optprobe_template_restore_end\n"
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"optprobe_template_restore_end:\n"
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" nop\n"
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".global optprobe_template_val\n"
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"optprobe_template_val:\n"
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"1: .long 0\n"
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".global optprobe_template_call\n"
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"optprobe_template_call:\n"
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"2: .long 0\n"
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".global optprobe_template_end\n"
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"optprobe_template_end:\n");
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#define TMPL_VAL_IDX \
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((unsigned long *)optprobe_template_val - (unsigned long *)optprobe_template_entry)
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#define TMPL_CALL_IDX \
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((unsigned long *)optprobe_template_call - (unsigned long *)optprobe_template_entry)
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#define TMPL_END_IDX \
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((unsigned long *)optprobe_template_end - (unsigned long *)optprobe_template_entry)
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#define TMPL_ADD_SP \
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((unsigned long *)optprobe_template_add_sp - (unsigned long *)optprobe_template_entry)
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#define TMPL_SUB_SP \
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((unsigned long *)optprobe_template_sub_sp - (unsigned long *)optprobe_template_entry)
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#define TMPL_RESTORE_BEGIN \
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((unsigned long *)optprobe_template_restore_begin - (unsigned long *)optprobe_template_entry)
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#define TMPL_RESTORE_ORIGN_INSN \
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((unsigned long *)optprobe_template_restore_orig_insn - (unsigned long *)optprobe_template_entry)
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#define TMPL_RESTORE_END \
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((unsigned long *)optprobe_template_restore_end - (unsigned long *)optprobe_template_entry)
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/*
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* ARM can always optimize an instruction when using ARM ISA, except
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* instructions like 'str r0, [sp, r1]' which store to stack and unable
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* to determine stack space consumption statically.
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*/
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int arch_prepared_optinsn(struct arch_optimized_insn *optinsn)
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{
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return optinsn->insn != NULL;
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}
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/*
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* In ARM ISA, kprobe opt always replace one instruction (4 bytes
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* aligned and 4 bytes long). It is impossible to encounter another
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* kprobe in the address range. So always return 0.
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*/
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int arch_check_optimized_kprobe(struct optimized_kprobe *op)
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{
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return 0;
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}
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/* Caller must ensure addr & 3 == 0 */
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static int can_optimize(struct kprobe *kp)
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{
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if (kp->ainsn.stack_space < 0)
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return 0;
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/*
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* 255 is the biggest imm can be used in 'sub r0, r0, #<imm>'.
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* Number larger than 255 needs special encoding.
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*/
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if (kp->ainsn.stack_space > 255 - sizeof(struct pt_regs))
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return 0;
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return 1;
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}
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/* Free optimized instruction slot */
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static void
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__arch_remove_optimized_kprobe(struct optimized_kprobe *op, int dirty)
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{
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if (op->optinsn.insn) {
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free_optinsn_slot(op->optinsn.insn, dirty);
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op->optinsn.insn = NULL;
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}
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}
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extern void kprobe_handler(struct pt_regs *regs);
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static void
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optimized_callback(struct optimized_kprobe *op, struct pt_regs *regs)
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{
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unsigned long flags;
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struct kprobe *p = &op->kp;
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struct kprobe_ctlblk *kcb;
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/* Save skipped registers */
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regs->ARM_pc = (unsigned long)op->kp.addr;
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regs->ARM_ORIG_r0 = ~0UL;
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local_irq_save(flags);
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kcb = get_kprobe_ctlblk();
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if (kprobe_running()) {
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kprobes_inc_nmissed_count(&op->kp);
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} else {
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__this_cpu_write(current_kprobe, &op->kp);
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kcb->kprobe_status = KPROBE_HIT_ACTIVE;
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opt_pre_handler(&op->kp, regs);
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__this_cpu_write(current_kprobe, NULL);
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}
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/*
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* We singlestep the replaced instruction only when it can't be
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* executed directly during restore.
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*/
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if (!p->ainsn.kprobe_direct_exec)
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op->kp.ainsn.insn_singlestep(p->opcode, &p->ainsn, regs);
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local_irq_restore(flags);
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}
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NOKPROBE_SYMBOL(optimized_callback)
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int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *orig)
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{
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kprobe_opcode_t *code;
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unsigned long rel_chk;
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unsigned long val;
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unsigned long stack_protect = sizeof(struct pt_regs);
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if (!can_optimize(orig))
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return -EILSEQ;
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code = get_optinsn_slot();
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if (!code)
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return -ENOMEM;
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/*
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* Verify if the address gap is in 32MiB range, because this uses
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* a relative jump.
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*
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* kprobe opt use a 'b' instruction to branch to optinsn.insn.
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* According to ARM manual, branch instruction is:
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*
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* 31 28 27 24 23 0
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* +------+---+---+---+---+----------------+
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* | cond | 1 | 0 | 1 | 0 | imm24 |
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* +------+---+---+---+---+----------------+
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*
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* imm24 is a signed 24 bits integer. The real branch offset is computed
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* by: imm32 = SignExtend(imm24:'00', 32);
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*
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* So the maximum forward branch should be:
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* (0x007fffff << 2) = 0x01fffffc = 0x1fffffc
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* The maximum backword branch should be:
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* (0xff800000 << 2) = 0xfe000000 = -0x2000000
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*
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* We can simply check (rel & 0xfe000003):
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* if rel is positive, (rel & 0xfe000000) shoule be 0
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* if rel is negitive, (rel & 0xfe000000) should be 0xfe000000
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* the last '3' is used for alignment checking.
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*/
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rel_chk = (unsigned long)((long)code -
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(long)orig->addr + 8) & 0xfe000003;
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if ((rel_chk != 0) && (rel_chk != 0xfe000000)) {
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/*
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* Different from x86, we free code buf directly instead of
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* calling __arch_remove_optimized_kprobe() because
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* we have not fill any field in op.
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*/
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free_optinsn_slot(code, 0);
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return -ERANGE;
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}
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/* Copy arch-dep-instance from template. */
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memcpy(code, (unsigned long *)optprobe_template_entry,
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TMPL_END_IDX * sizeof(kprobe_opcode_t));
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/* Adjust buffer according to instruction. */
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BUG_ON(orig->ainsn.stack_space < 0);
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stack_protect += orig->ainsn.stack_space;
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/* Should have been filtered by can_optimize(). */
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BUG_ON(stack_protect > 255);
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/* Create a 'sub sp, sp, #<stack_protect>' */
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code[TMPL_SUB_SP] = __opcode_to_mem_arm(0xe24dd000 | stack_protect);
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/* Create a 'add r3, sp, #<stack_protect>' */
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code[TMPL_ADD_SP] = __opcode_to_mem_arm(0xe28d3000 | stack_protect);
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/* Set probe information */
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val = (unsigned long)op;
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code[TMPL_VAL_IDX] = val;
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/* Set probe function call */
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val = (unsigned long)optimized_callback;
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code[TMPL_CALL_IDX] = val;
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/* If possible, copy insn and have it executed during restore */
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orig->ainsn.kprobe_direct_exec = false;
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if (can_kprobe_direct_exec(orig->ainsn.register_usage_flags)) {
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kprobe_opcode_t final_branch = arm_gen_branch(
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(unsigned long)(&code[TMPL_RESTORE_END]),
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(unsigned long)(op->kp.addr) + 4);
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if (final_branch != 0) {
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/*
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* Replace original 'ldmia sp, {r0 - r15}' with
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* 'ldmia {r0 - r14}', restore all registers except pc.
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*/
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code[TMPL_RESTORE_BEGIN] = __opcode_to_mem_arm(0xe89d7fff);
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/* The original probed instruction */
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code[TMPL_RESTORE_ORIGN_INSN] = __opcode_to_mem_arm(orig->opcode);
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/* Jump back to next instruction */
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code[TMPL_RESTORE_END] = __opcode_to_mem_arm(final_branch);
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orig->ainsn.kprobe_direct_exec = true;
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}
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}
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flush_icache_range((unsigned long)code,
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(unsigned long)(&code[TMPL_END_IDX]));
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/* Set op->optinsn.insn means prepared. */
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op->optinsn.insn = code;
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return 0;
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}
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void __kprobes arch_optimize_kprobes(struct list_head *oplist)
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{
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struct optimized_kprobe *op, *tmp;
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list_for_each_entry_safe(op, tmp, oplist, list) {
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unsigned long insn;
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WARN_ON(kprobe_disabled(&op->kp));
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/*
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* Backup instructions which will be replaced
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* by jump address
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*/
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memcpy(op->optinsn.copied_insn, op->kp.addr,
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RELATIVEJUMP_SIZE);
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insn = arm_gen_branch((unsigned long)op->kp.addr,
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(unsigned long)op->optinsn.insn);
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BUG_ON(insn == 0);
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/*
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* Make it a conditional branch if replaced insn
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* is consitional
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*/
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insn = (__mem_to_opcode_arm(
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op->optinsn.copied_insn[0]) & 0xf0000000) |
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(insn & 0x0fffffff);
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/*
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* Similar to __arch_disarm_kprobe, operations which
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* removing breakpoints must be wrapped by stop_machine
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* to avoid racing.
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*/
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kprobes_remove_breakpoint(op->kp.addr, insn);
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list_del_init(&op->list);
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}
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}
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void arch_unoptimize_kprobe(struct optimized_kprobe *op)
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{
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arch_arm_kprobe(&op->kp);
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}
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/*
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* Recover original instructions and breakpoints from relative jumps.
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* Caller must call with locking kprobe_mutex.
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*/
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void arch_unoptimize_kprobes(struct list_head *oplist,
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struct list_head *done_list)
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{
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struct optimized_kprobe *op, *tmp;
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list_for_each_entry_safe(op, tmp, oplist, list) {
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arch_unoptimize_kprobe(op);
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list_move(&op->list, done_list);
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}
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}
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int arch_within_optimized_kprobe(struct optimized_kprobe *op,
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kprobe_opcode_t *addr)
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{
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return (op->kp.addr <= addr &&
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op->kp.addr + (RELATIVEJUMP_SIZE / sizeof(kprobe_opcode_t)) > addr);
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}
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void arch_remove_optimized_kprobe(struct optimized_kprobe *op)
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{
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|
__arch_remove_optimized_kprobe(op, 1);
|
||
|
|
}
|