238 lines
6.8 KiB
C
238 lines
6.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP2/3 PRM module functions
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*
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* Copyright (C) 2010-2011 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "powerdomain.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
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#include "clockdomain.h"
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/**
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* omap2_prm_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @shift: register bit shift corresponding to the reset line to check
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* @part: PRM partition, ignored for OMAP2
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @offset: register offset, ignored for OMAP2
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL if called while running on a non-OMAP2/3 chip.
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*/
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int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
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{
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return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
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(1 << shift));
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}
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/**
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* omap2_prm_assert_hardreset - assert the HW reset line of a submodule
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* @shift: register bit shift corresponding to the reset line to assert
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* @part: PRM partition, ignored for OMAP2
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @offset: register offset, ignored for OMAP2
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*
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* Some IPs like dsp or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
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{
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u32 mask;
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mask = 1 << shift;
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omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
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return 0;
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}
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/**
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* omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @rst_shift: register bit shift corresponding to the reset line to deassert
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* @st_shift: register bit shift for the status of the deasserted submodule
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* @part: PRM partition, not used for OMAP2
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @rst_offset: reset register offset, not used for OMAP2
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* @st_offset: reset status register offset, not used for OMAP2
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*
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* Some IPs like dsp or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
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s16 prm_mod, u16 rst_offset, u16 st_offset)
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{
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u32 rst, st;
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int c;
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rst = 1 << rst_shift;
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st = 1 << st_shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
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/* de-assert the reset control line */
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omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
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/* wait the status to be set */
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omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
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st),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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/* Powerdomain low-level functions */
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/* Common functions across OMAP2 and OMAP3 */
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int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
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m);
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}
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int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL, m);
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}
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int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
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{
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u32 v;
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v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
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omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
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{
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u32 c = 0;
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/*
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* REVISIT: pwrdm_wait_transition() may be better implemented
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* via a callback and a periodic timer check -- how long do we expect
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* powerdomain transitions to take?
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*/
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/* XXX Is this udelay() value meaningful? */
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while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
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OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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pr_err("powerdomain: %s: waited too long to complete transition\n",
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pwrdm->name);
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return -EAGAIN;
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}
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pr_debug("powerdomain: completed transition in %d loops\n", c);
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return 0;
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}
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int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
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return 0;
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}
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int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
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return 0;
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}
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int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
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PM_WKDEP, (1 << clkdm2->dep_bit));
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}
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/* XXX Caller must hold the clkdm's powerdomain lock */
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int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
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{
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struct clkdm_dep *cd;
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u32 mask = 0;
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for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
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if (!cd->clkdm)
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continue; /* only happens if data is erroneous */
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/* PRM accesses are slow, so minimize them */
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mask |= 1 << cd->clkdm->dep_bit;
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cd->wkdep_usecount = 0;
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}
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omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
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PM_WKDEP);
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return 0;
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}
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