280 lines
6.2 KiB
C
280 lines
6.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_CMPXCHG_H
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#define __ASM_ARM_CMPXCHG_H
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#include <linux/irqflags.h>
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#include <linux/prefetch.h>
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#include <asm/barrier.h>
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#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
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/*
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* On the StrongARM, "swp" is terminally broken since it bypasses the
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* cache totally. This means that the cache becomes inconsistent, and,
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* since we use normal loads/stores as well, this is really bad.
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* Typically, this causes oopsen in filp_close, but could have other,
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* more disastrous effects. There are two work-arounds:
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* 1. Disable interrupts and emulate the atomic swap
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* 2. Clean the cache, perform atomic swap, flush the cache
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*
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* We choose (1) since its the "easiest" to achieve here and is not
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* dependent on the processor type.
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*
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* NOTE that this solution won't work on an SMP system, so explcitly
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* forbid it here.
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*/
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#define swp_is_buggy
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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unsigned long ret;
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#ifdef swp_is_buggy
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unsigned long flags;
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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unsigned int tmp;
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#endif
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prefetchw((const void *)ptr);
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switch (size) {
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#if __LINUX_ARM_ARCH__ >= 6
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#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
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case 1:
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asm volatile("@ __xchg1\n"
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"1: ldrexb %0, [%3]\n"
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" strexb %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 2:
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asm volatile("@ __xchg2\n"
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"1: ldrexh %0, [%3]\n"
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" strexh %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#endif
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case 4:
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asm volatile("@ __xchg4\n"
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"1: ldrex %0, [%3]\n"
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" strex %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#elif defined(swp_is_buggy)
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#ifdef CONFIG_SMP
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#error SMP is not supported on this platform
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#endif
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case 1:
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raw_local_irq_save(flags);
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ret = *(volatile unsigned char *)ptr;
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*(volatile unsigned char *)ptr = x;
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raw_local_irq_restore(flags);
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break;
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case 4:
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raw_local_irq_save(flags);
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ret = *(volatile unsigned long *)ptr;
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*(volatile unsigned long *)ptr = x;
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raw_local_irq_restore(flags);
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break;
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#else
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case 1:
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asm volatile("@ __xchg1\n"
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" swpb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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" swp %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#endif
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default:
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/* Cause a link-time error, the xchg() size is not supported */
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__bad_xchg(ptr, size), ret = 0;
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break;
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}
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return ret;
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}
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#define arch_xchg_relaxed(ptr, x) ({ \
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(__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
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sizeof(*(ptr))); \
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})
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#include <asm-generic/cmpxchg-local.h>
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#if __LINUX_ARM_ARCH__ < 6
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/* min ARCH < ARMv6 */
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#ifdef CONFIG_SMP
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#error "SMP is not supported on this platform"
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#endif
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#define arch_xchg arch_xchg_relaxed
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define arch_cmpxchg_local(ptr, o, n) ({ \
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(__typeof(*ptr))__generic_cmpxchg_local((ptr), \
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(unsigned long)(o), \
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(unsigned long)(n), \
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sizeof(*(ptr))); \
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})
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#define arch_cmpxchg64_local(ptr, o, n) __generic_cmpxchg64_local((ptr), (o), (n))
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#include <asm-generic/cmpxchg.h>
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#else /* min ARCH >= ARMv6 */
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extern void __bad_cmpxchg(volatile void *ptr, int size);
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/*
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* cmpxchg only support 32-bits operands on ARMv6.
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*/
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long oldval, res;
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prefetchw((const void *)ptr);
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switch (size) {
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#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
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case 1:
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do {
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asm volatile("@ __cmpxchg1\n"
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" ldrexb %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexbeq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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case 2:
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do {
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asm volatile("@ __cmpxchg1\n"
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" ldrexh %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexheq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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#endif
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case 4:
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do {
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asm volatile("@ __cmpxchg4\n"
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" ldrex %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexeq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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default:
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__bad_cmpxchg(ptr, size);
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oldval = 0;
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}
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return oldval;
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}
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#define arch_cmpxchg_relaxed(ptr,o,n) ({ \
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(__typeof__(*(ptr)))__cmpxchg((ptr), \
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(unsigned long)(o), \
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(unsigned long)(n), \
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sizeof(*(ptr))); \
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})
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long ret;
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switch (size) {
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#ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
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case 1:
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case 2:
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ret = __generic_cmpxchg_local(ptr, old, new, size);
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break;
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#endif
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default:
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ret = __cmpxchg(ptr, old, new, size);
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}
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return ret;
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}
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#define arch_cmpxchg_local(ptr, o, n) ({ \
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(__typeof(*ptr))__cmpxchg_local((ptr), \
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(unsigned long)(o), \
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(unsigned long)(n), \
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sizeof(*(ptr))); \
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})
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static inline unsigned long long __cmpxchg64(unsigned long long *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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unsigned long long oldval;
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unsigned long res;
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prefetchw(ptr);
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__asm__ __volatile__(
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"1: ldrexd %1, %H1, [%3]\n"
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" teq %1, %4\n"
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" teqeq %H1, %H4\n"
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" bne 2f\n"
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" strexd %0, %5, %H5, [%3]\n"
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" teq %0, #0\n"
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" bne 1b\n"
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"2:"
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: "=&r" (res), "=&r" (oldval), "+Qo" (*ptr)
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: "r" (ptr), "r" (old), "r" (new)
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: "cc");
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return oldval;
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}
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#define arch_cmpxchg64_relaxed(ptr, o, n) ({ \
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(__typeof__(*(ptr)))__cmpxchg64((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)); \
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})
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#define arch_cmpxchg64_local(ptr, o, n) arch_cmpxchg64_relaxed((ptr), (o), (n))
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#endif /* __LINUX_ARM_ARCH__ >= 6 */
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#endif /* __ASM_ARM_CMPXCHG_H */
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