520 lines
12 KiB
Plaintext
520 lines
12 KiB
Plaintext
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/qcom,gcc-msm8974.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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chosen { };
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8226", "qcom,scm";
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clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
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clock-names = "core", "bus", "iface";
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x80>;
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#hwlock-cells = <1>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_region: smem@3000000 {
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reg = <0x3000000 0x100000>;
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no-map;
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};
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};
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8226";
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qcom,smd-channels = "rpm_requests";
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rpmpd: power-controller {
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compatible = "qcom,msm8226-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_ret: opp1 {
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opp-level = <1>;
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};
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rpmpd_opp_svs_krait: opp2 {
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opp-level = <2>;
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};
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rpmpd_opp_svs_soc: opp3 {
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opp-level = <3>;
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};
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rpmpd_opp_nom: opp4 {
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opp-level = <4>;
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};
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rpmpd_opp_turbo: opp5 {
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opp-level = <5>;
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};
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rpmpd_opp_super_turbo: opp6 {
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opp-level = <6>;
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};
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};
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};
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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apcs: syscon@f9011000 {
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compatible = "syscon";
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reg = <0xf9011000 0x1000>;
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};
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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pinctrl-names = "default";
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pinctrl-0 = <&sdhc1_default_state>;
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status = "disabled";
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};
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sdhc_2: sdhci@f98a4900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>,
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<&gcc GCC_SDCC2_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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pinctrl-names = "default";
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pinctrl-0 = <&sdhc2_default_state>;
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status = "disabled";
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};
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sdhc_3: sdhci@f9864900 {
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compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC3_APPS_CLK>,
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<&gcc GCC_SDCC3_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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pinctrl-names = "default";
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pinctrl-0 = <&sdhc3_default_state>;
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status = "disabled";
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};
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blsp1_uart3: serial@f991f000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991f000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_uart4: serial@f9920000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf9920000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_i2c1: i2c@f9923000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9923000 0x1000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c1_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c2: i2c@f9924000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9924000 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c2_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c3: i2c@f9925000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9925000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c3_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c4: i2c@f9926000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9926000 0x1000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c4_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c5: i2c@f9927000 {
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status = "disabled";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9927000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_i2c5_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb: usb@f9a55000 {
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compatible = "qcom,ci-hdrc";
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reg = <0xf9a55000 0x200>,
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<0xf9a55200 0x200>;
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_USB_HS_AHB_CLK>,
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<&gcc GCC_USB_HS_SYSTEM_CLK>;
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clock-names = "iface", "core";
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assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
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assigned-clock-rates = <75000000>;
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resets = <&gcc GCC_USB_HS_BCR>;
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reset-names = "core";
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phy_type = "ulpi";
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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ahb-burst-config = <0>;
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phy-names = "usb-phy";
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phys = <&usb_hs_phy>;
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status = "disabled";
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#reset-cells = <1>;
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ulpi {
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usb_hs_phy: phy {
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compatible = "qcom,usb-hs-phy-msm8226",
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"qcom,usb-hs-phy";
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#phy-cells = <0>;
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clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref", "sleep";
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
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reset-names = "phy", "por";
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qcom,init-seq = /bits/ 8 <0x0 0x44
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0x1 0x68 0x2 0x24 0x3 0x13>;
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};
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};
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-msm8226";
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reg = <0xfc400000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,msm8226-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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blsp1_i2c1_pins: blsp1-i2c1 {
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pins = "gpio2", "gpio3";
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function = "blsp_i2c1";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c2_pins: blsp1-i2c2 {
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pins = "gpio6", "gpio7";
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function = "blsp_i2c2";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c3_pins: blsp1-i2c3 {
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pins = "gpio10", "gpio11";
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function = "blsp_i2c3";
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drive-strength = <2>;
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bias-disable;
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};
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blsp1_i2c4_pins: blsp1-i2c4 {
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pins = "gpio14", "gpio15";
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function = "blsp_i2c4";
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drive-strength = <2>;
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bias-disable;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_i2c5_pins: blsp1-i2c5 {
|
||
|
|
pins = "gpio18", "gpio19";
|
||
|
|
function = "blsp_i2c5";
|
||
|
|
drive-strength = <2>;
|
||
|
|
bias-disable;
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc1_default_state: sdhc1-default-state {
|
||
|
|
clk {
|
||
|
|
pins = "sdc1_clk";
|
||
|
|
drive-strength = <10>;
|
||
|
|
bias-disable;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd-data {
|
||
|
|
pins = "sdc1_cmd", "sdc1_data";
|
||
|
|
drive-strength = <10>;
|
||
|
|
bias-pull-up;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc2_default_state: sdhc2-default-state {
|
||
|
|
clk {
|
||
|
|
pins = "sdc2_clk";
|
||
|
|
drive-strength = <10>;
|
||
|
|
bias-disable;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd-data {
|
||
|
|
pins = "sdc2_cmd", "sdc2_data";
|
||
|
|
drive-strength = <10>;
|
||
|
|
bias-pull-up;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc3_default_state: sdhc3-default-state {
|
||
|
|
clk {
|
||
|
|
pins = "gpio44";
|
||
|
|
function = "sdc3";
|
||
|
|
drive-strength = <8>;
|
||
|
|
bias-disable;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd {
|
||
|
|
pins = "gpio43";
|
||
|
|
function = "sdc3";
|
||
|
|
drive-strength = <8>;
|
||
|
|
bias-pull-up;
|
||
|
|
};
|
||
|
|
|
||
|
|
data {
|
||
|
|
pins = "gpio39", "gpio40", "gpio41", "gpio42";
|
||
|
|
function = "sdc3";
|
||
|
|
drive-strength = <8>;
|
||
|
|
bias-pull-up;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
restart@fc4ab000 {
|
||
|
|
compatible = "qcom,pshold";
|
||
|
|
reg = <0xfc4ab000 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spmi_bus: spmi@fc4cf000 {
|
||
|
|
compatible = "qcom,spmi-pmic-arb";
|
||
|
|
reg-names = "core", "intr", "cnfg";
|
||
|
|
reg = <0xfc4cf000 0x1000>,
|
||
|
|
<0xfc4cb000 0x1000>,
|
||
|
|
<0xfc4ca000 0x1000>;
|
||
|
|
interrupt-names = "periph_irq";
|
||
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,ee = <0>;
|
||
|
|
qcom,channel = <0>;
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rng@f9bff000 {
|
||
|
|
compatible = "qcom,prng";
|
||
|
|
reg = <0xf9bff000 0x200>;
|
||
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||
|
|
clock-names = "core";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@f9020000 {
|
||
|
|
compatible = "arm,armv7-timer-mem";
|
||
|
|
reg = <0xf9020000 0x1000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
frame@f9021000 {
|
||
|
|
frame-number = <0>;
|
||
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9021000 0x1000>,
|
||
|
|
<0xf9022000 0x1000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9023000 {
|
||
|
|
frame-number = <1>;
|
||
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9023000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9024000 {
|
||
|
|
frame-number = <2>;
|
||
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9024000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9025000 {
|
||
|
|
frame-number = <3>;
|
||
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9025000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9026000 {
|
||
|
|
frame-number = <4>;
|
||
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9026000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9027000 {
|
||
|
|
frame-number = <5>;
|
||
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9027000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@f9028000 {
|
||
|
|
frame-number = <6>;
|
||
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0xf9028000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
rpm_msg_ram: memory@fc428000 {
|
||
|
|
compatible = "qcom,rpm-msg-ram";
|
||
|
|
reg = <0xfc428000 0x4000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
tcsr_mutex_block: syscon@fd484000 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0xfd484000 0x2000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timer {
|
||
|
|
compatible = "arm,armv7-timer";
|
||
|
|
interrupts = <GIC_PPI 2
|
||
|
|
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 3
|
||
|
|
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 4
|
||
|
|
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 1
|
||
|
|
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
|
||
|
|
};
|
||
|
|
};
|