392 lines
13 KiB
ReStructuredText
392 lines
13 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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=================
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KVM-specific MSRs
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=================
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:Author: Glauber Costa <glommer@redhat.com>, Red Hat Inc, 2010
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KVM makes use of some custom MSRs to service some requests.
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Custom MSRs have a range reserved for them, that goes from
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0x4b564d00 to 0x4b564dff. There are MSRs outside this area,
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but they are deprecated and their use is discouraged.
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Custom MSR list
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---------------
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The current supported Custom MSR list is:
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MSR_KVM_WALL_CLOCK_NEW:
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0x4b564d00
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data:
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4-byte alignment physical address of a memory area which must be
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in guest RAM. This memory is expected to hold a copy of the following
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structure::
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struct pvclock_wall_clock {
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u32 version;
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u32 sec;
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u32 nsec;
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} __attribute__((__packed__));
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whose data will be filled in by the hypervisor. The hypervisor is only
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guaranteed to update this data at the moment of MSR write.
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Users that want to reliably query this information more than once have
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to write more than once to this MSR. Fields have the following meanings:
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version:
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guest has to check version before and after grabbing
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time information and check that they are both equal and even.
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An odd version indicates an in-progress update.
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sec:
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number of seconds for wallclock at time of boot.
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nsec:
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number of nanoseconds for wallclock at time of boot.
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In order to get the current wallclock time, the system_time from
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MSR_KVM_SYSTEM_TIME_NEW needs to be added.
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Note that although MSRs are per-CPU entities, the effect of this
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particular MSR is global.
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Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_SYSTEM_TIME_NEW:
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0x4b564d01
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data:
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4-byte aligned physical address of a memory area which must be in
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guest RAM, plus an enable bit in bit 0. This memory is expected to hold
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a copy of the following structure::
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struct pvclock_vcpu_time_info {
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u32 version;
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u32 pad0;
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u64 tsc_timestamp;
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u64 system_time;
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u32 tsc_to_system_mul;
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s8 tsc_shift;
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u8 flags;
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u8 pad[2];
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} __attribute__((__packed__)); /* 32 bytes */
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whose data will be filled in by the hypervisor periodically. Only one
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write, or registration, is needed for each VCPU. The interval between
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updates of this structure is arbitrary and implementation-dependent.
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The hypervisor may update this structure at any time it sees fit until
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anything with bit0 == 0 is written to it.
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Fields have the following meanings:
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version:
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guest has to check version before and after grabbing
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time information and check that they are both equal and even.
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An odd version indicates an in-progress update.
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tsc_timestamp:
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the tsc value at the current VCPU at the time
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of the update of this structure. Guests can subtract this value
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from current tsc to derive a notion of elapsed time since the
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structure update.
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system_time:
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a host notion of monotonic time, including sleep
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time at the time this structure was last updated. Unit is
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nanoseconds.
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tsc_to_system_mul:
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multiplier to be used when converting
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tsc-related quantity to nanoseconds
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tsc_shift:
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shift to be used when converting tsc-related
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quantity to nanoseconds. This shift will ensure that
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multiplication with tsc_to_system_mul does not overflow.
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A positive value denotes a left shift, a negative value
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a right shift.
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The conversion from tsc to nanoseconds involves an additional
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right shift by 32 bits. With this information, guests can
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derive per-CPU time by doing::
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time = (current_tsc - tsc_timestamp)
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if (tsc_shift >= 0)
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time <<= tsc_shift;
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else
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time >>= -tsc_shift;
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time = (time * tsc_to_system_mul) >> 32
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time = time + system_time
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flags:
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bits in this field indicate extended capabilities
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coordinated between the guest and the hypervisor. Availability
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of specific flags has to be checked in 0x40000001 cpuid leaf.
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Current flags are:
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+-----------+--------------+----------------------------------+
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| flag bit | cpuid bit | meaning |
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+-----------+--------------+----------------------------------+
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| | | time measures taken across |
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| 0 | 24 | multiple cpus are guaranteed to |
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| | | be monotonic |
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+-----------+--------------+----------------------------------+
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| | | guest vcpu has been paused by |
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| 1 | N/A | the host |
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| | | See 4.70 in api.txt |
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+-----------+--------------+----------------------------------+
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Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_WALL_CLOCK:
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0x11
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data and functioning:
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same as MSR_KVM_WALL_CLOCK_NEW. Use that instead.
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This MSR falls outside the reserved KVM range and may be removed in the
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future. Its usage is deprecated.
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Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_SYSTEM_TIME:
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0x12
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data and functioning:
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same as MSR_KVM_SYSTEM_TIME_NEW. Use that instead.
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This MSR falls outside the reserved KVM range and may be removed in the
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future. Its usage is deprecated.
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Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
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leaf prior to usage.
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The suggested algorithm for detecting kvmclock presence is then::
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if (!kvm_para_available()) /* refer to cpuid.txt */
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return NON_PRESENT;
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flags = cpuid_eax(0x40000001);
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if (flags & 3) {
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msr_kvm_system_time = MSR_KVM_SYSTEM_TIME_NEW;
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msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK_NEW;
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return PRESENT;
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} else if (flags & 0) {
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msr_kvm_system_time = MSR_KVM_SYSTEM_TIME;
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msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK;
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return PRESENT;
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} else
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return NON_PRESENT;
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MSR_KVM_ASYNC_PF_EN:
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0x4b564d02
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data:
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Asynchronous page fault (APF) control MSR.
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Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
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which must be in guest RAM and must be zeroed. This memory is expected
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to hold a copy of the following structure::
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struct kvm_vcpu_pv_apf_data {
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/* Used for 'page not present' events delivered via #PF */
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__u32 flags;
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/* Used for 'page ready' events delivered via interrupt notification */
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__u32 token;
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__u8 pad[56];
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__u32 enabled;
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};
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Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
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when asynchronous page faults are enabled on the vcpu, 0 when disabled.
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Bit 1 is 1 if asynchronous page faults can be injected when vcpu is in
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cpl == 0. Bit 2 is 1 if asynchronous page faults are delivered to L1 as
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#PF vmexits. Bit 2 can be set only if KVM_FEATURE_ASYNC_PF_VMEXIT is
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present in CPUID. Bit 3 enables interrupt based delivery of 'page ready'
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events. Bit 3 can only be set if KVM_FEATURE_ASYNC_PF_INT is present in
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CPUID.
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'Page not present' events are currently always delivered as synthetic
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#PF exception. During delivery of these events APF CR2 register contains
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a token that will be used to notify the guest when missing page becomes
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available. Also, to make it possible to distinguish between real #PF and
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APF, first 4 bytes of 64 byte memory location ('flags') will be written
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to by the hypervisor at the time of injection. Only first bit of 'flags'
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is currently supported, when set, it indicates that the guest is dealing
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with asynchronous 'page not present' event. If during a page fault APF
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'flags' is '0' it means that this is regular page fault. Guest is
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supposed to clear 'flags' when it is done handling #PF exception so the
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next event can be delivered.
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Note, since APF 'page not present' events use the same exception vector
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as regular page fault, guest must reset 'flags' to '0' before it does
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something that can generate normal page fault.
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Bytes 5-7 of 64 byte memory location ('token') will be written to by the
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hypervisor at the time of APF 'page ready' event injection. The content
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of these bytes is a token which was previously delivered as 'page not
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present' event. The event indicates the page in now available. Guest is
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supposed to write '0' to 'token' when it is done handling 'page ready'
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event and to write 1' to MSR_KVM_ASYNC_PF_ACK after clearing the location;
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writing to the MSR forces KVM to re-scan its queue and deliver the next
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pending notification.
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Note, MSR_KVM_ASYNC_PF_INT MSR specifying the interrupt vector for 'page
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ready' APF delivery needs to be written to before enabling APF mechanism
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in MSR_KVM_ASYNC_PF_EN or interrupt #0 can get injected. The MSR is
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available if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
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Note, previously, 'page ready' events were delivered via the same #PF
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exception as 'page not present' events but this is now deprecated. If
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bit 3 (interrupt based delivery) is not set APF events are not delivered.
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If APF is disabled while there are outstanding APFs, they will
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not be delivered.
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Currently 'page ready' APF events will be always delivered on the
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same vcpu as 'page not present' event was, but guest should not rely on
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that.
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MSR_KVM_STEAL_TIME:
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0x4b564d03
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data:
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64-byte alignment physical address of a memory area which must be
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in guest RAM, plus an enable bit in bit 0. This memory is expected to
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hold a copy of the following structure::
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struct kvm_steal_time {
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__u64 steal;
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__u32 version;
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__u32 flags;
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__u8 preempted;
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__u8 u8_pad[3];
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__u32 pad[11];
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}
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whose data will be filled in by the hypervisor periodically. Only one
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write, or registration, is needed for each VCPU. The interval between
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updates of this structure is arbitrary and implementation-dependent.
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The hypervisor may update this structure at any time it sees fit until
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anything with bit0 == 0 is written to it. Guest is required to make sure
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this structure is initialized to zero.
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Fields have the following meanings:
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version:
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a sequence counter. In other words, guest has to check
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this field before and after grabbing time information and make
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sure they are both equal and even. An odd version indicates an
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in-progress update.
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flags:
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At this point, always zero. May be used to indicate
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changes in this structure in the future.
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steal:
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the amount of time in which this vCPU did not run, in
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nanoseconds. Time during which the vcpu is idle, will not be
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reported as steal time.
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preempted:
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indicate the vCPU who owns this struct is running or
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not. Non-zero values mean the vCPU has been preempted. Zero
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means the vCPU is not preempted. NOTE, it is always zero if the
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the hypervisor doesn't support this field.
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MSR_KVM_EOI_EN:
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0x4b564d04
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data:
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Bit 0 is 1 when PV end of interrupt is enabled on the vcpu; 0
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when disabled. Bit 1 is reserved and must be zero. When PV end of
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interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
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physical address of a 4 byte memory area which must be in guest RAM and
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must be zeroed.
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The first, least significant bit of 4 byte memory location will be
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written to by the hypervisor, typically at the time of interrupt
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injection. Value of 1 means that guest can skip writing EOI to the apic
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(using MSR or MMIO write); instead, it is sufficient to signal
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EOI by clearing the bit in guest memory - this location will
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later be polled by the hypervisor.
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Value of 0 means that the EOI write is required.
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It is always safe for the guest to ignore the optimization and perform
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the APIC EOI write anyway.
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Hypervisor is guaranteed to only modify this least
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significant bit while in the current VCPU context, this means that
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guest does not need to use either lock prefix or memory ordering
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primitives to synchronise with the hypervisor.
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However, hypervisor can set and clear this memory bit at any time:
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therefore to make sure hypervisor does not interrupt the
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guest and clear the least significant bit in the memory area
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in the window between guest testing it to detect
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whether it can skip EOI apic write and between guest
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clearing it to signal EOI to the hypervisor,
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guest must both read the least significant bit in the memory area and
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clear it using a single CPU instruction, such as test and clear, or
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compare and exchange.
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MSR_KVM_POLL_CONTROL:
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0x4b564d05
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Control host-side polling.
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data:
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Bit 0 enables (1) or disables (0) host-side HLT polling logic.
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KVM guests can request the host not to poll on HLT, for example if
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they are performing polling themselves.
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MSR_KVM_ASYNC_PF_INT:
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0x4b564d06
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data:
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Second asynchronous page fault (APF) control MSR.
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Bits 0-7: APIC vector for delivery of 'page ready' APF events.
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Bits 8-63: Reserved
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Interrupt vector for asynchnonous 'page ready' notifications delivery.
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The vector has to be set up before asynchronous page fault mechanism
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is enabled in MSR_KVM_ASYNC_PF_EN. The MSR is only available if
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KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
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MSR_KVM_ASYNC_PF_ACK:
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0x4b564d07
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data:
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Asynchronous page fault (APF) acknowledgment.
|
||
|
|
|
||
|
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When the guest is done processing 'page ready' APF event and 'token'
|
||
|
|
field in 'struct kvm_vcpu_pv_apf_data' is cleared it is supposed to
|
||
|
|
write '1' to bit 0 of the MSR, this causes the host to re-scan its queue
|
||
|
|
and check if there are more notifications pending. The MSR is available
|
||
|
|
if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
|
||
|
|
|
||
|
|
MSR_KVM_MIGRATION_CONTROL:
|
||
|
|
0x4b564d08
|
||
|
|
|
||
|
|
data:
|
||
|
|
This MSR is available if KVM_FEATURE_MIGRATION_CONTROL is present in
|
||
|
|
CPUID. Bit 0 represents whether live migration of the guest is allowed.
|
||
|
|
|
||
|
|
When a guest is started, bit 0 will be 0 if the guest has encrypted
|
||
|
|
memory and 1 if the guest does not have encrypted memory. If the
|
||
|
|
guest is communicating page encryption status to the host using the
|
||
|
|
``KVM_HC_MAP_GPA_RANGE`` hypercall, it can set bit 0 in this MSR to
|
||
|
|
allow live migration of the guest.
|