166 lines
6.0 KiB
Plaintext
166 lines
6.0 KiB
Plaintext
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What: /sys/bus/cxl/flush
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Date: Januarry, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) If userspace manually unbinds a port the kernel schedules
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all descendant memdevs for unbind. Writing '1' to this attribute
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flushes that work.
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What: /sys/bus/cxl/devices/memX/firmware_version
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "FW Revision" string as reported by the Identify
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Memory Device Output Payload in the CXL-2.0
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specification.
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What: /sys/bus/cxl/devices/memX/ram/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Volatile Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/memX/pmem/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Persistent Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/memX/serial
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) 64-bit serial number per the PCIe Device Serial Number
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capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
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Memory Device PCIe Capabilities and Extended Capabilities.
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What: /sys/bus/cxl/devices/memX/numa_node
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) If NUMA is enabled and the platform has affinitized the
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host PCI device for this memory device, emit the CPU node
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affinity for this device.
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What: /sys/bus/cxl/devices/*/devtype
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL device objects export the devtype attribute which mirrors
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the same value communicated in the DEVTYPE environment variable
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for uevents for devices on the "cxl" bus.
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What: /sys/bus/cxl/devices/*/modalias
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Date: December, 2021
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL device objects export the modalias attribute which mirrors
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the same value communicated in the MODALIAS environment variable
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for uevents for devices on the "cxl" bus.
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What: /sys/bus/cxl/devices/portX/uport
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL port objects are enumerated from either a platform firmware
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device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
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CXL component registers. The 'uport' symlink connects the CXL
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portX object to the device that published the CXL port
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capability.
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What: /sys/bus/cxl/devices/portX/dportY
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL port objects are enumerated from either a platform firmware
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device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
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CXL component registers. The 'dportY' symlink identifies one or
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more downstream ports that the upstream port may target in its
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decode of CXL memory resources. The 'Y' integer reflects the
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hardware port unique-id used in the hardware decoder target
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list.
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What: /sys/bus/cxl/devices/decoderX.Y
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL decoder objects are enumerated from either a platform
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firmware description, or a CXL HDM decoder register set in a
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PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
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Capability Structure). The 'X' in decoderX.Y represents the
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cxl_port container of this decoder, and 'Y' represents the
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instance id of a given decoder resource.
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What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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The 'start' and 'size' attributes together convey the physical
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address base and number of bytes mapped in the decoder's decode
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window. For decoders of devtype "cxl_decoder_root" the address
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range is fixed. For decoders of devtype "cxl_decoder_switch" the
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address is bounded by the decode range of the cxl_port ancestor
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of the decoder's cxl_port, and dynamically updates based on the
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active memory regions in that address space.
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What: /sys/bus/cxl/devices/decoderX.Y/locked
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL HDM decoders have the capability to lock the configuration
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until the next device reset. For decoders of devtype
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"cxl_decoder_root" there is no standard facility to unlock them.
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For decoders of devtype "cxl_decoder_switch" a secondary bus
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reset, of the PCIe bridge that provides the bus for this
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decoders uport, unlocks / resets the decoder.
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What: /sys/bus/cxl/devices/decoderX.Y/target_list
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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Display a comma separated list of the current decoder target
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configuration. The list is ordered by the current configured
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interleave order of the decoder's dport instances. Each entry in
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the list is a dport id.
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What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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When a CXL decoder is of devtype "cxl_decoder_root", it
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represents a fixed memory window identified by platform
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firmware. A fixed window may only support a subset of memory
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types. The 'cap_*' attributes indicate whether persistent
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memory, volatile memory, accelerator memory, and / or expander
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memory may be mapped behind this decoder's memory window.
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What: /sys/bus/cxl/devices/decoderX.Y/target_type
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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When a CXL decoder is of devtype "cxl_decoder_switch", it can
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optionally decode either accelerator memory (type-2) or expander
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memory (type-3). The 'target_type' attribute indicates the
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current setting which may dynamically change based on what
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memory regions are activated in this decode hierarchy.
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