695 lines
14 KiB
C
695 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Performance event support - Freescale Embedded Performance Monitor
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/perf_event.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/reg_fsl_emb.h>
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#include <asm/pmc.h>
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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#include <asm/ptrace.h>
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struct cpu_hw_events {
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int n_events;
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int disabled;
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u8 pmcs_enabled;
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struct perf_event *event[MAX_HWEVENTS];
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};
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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static struct fsl_emb_pmu *ppmu;
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/* Number of perf_events counting hardware events */
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static atomic_t num_events;
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/* Used to avoid races in calling reserve/release_pmc_hardware */
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static DEFINE_MUTEX(pmc_reserve_mutex);
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static void perf_event_interrupt(struct pt_regs *regs);
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/*
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* Read one performance monitor counter (PMC).
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*/
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static unsigned long read_pmc(int idx)
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{
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unsigned long val;
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switch (idx) {
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case 0:
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val = mfpmr(PMRN_PMC0);
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break;
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case 1:
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val = mfpmr(PMRN_PMC1);
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break;
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case 2:
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val = mfpmr(PMRN_PMC2);
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break;
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case 3:
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val = mfpmr(PMRN_PMC3);
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break;
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case 4:
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val = mfpmr(PMRN_PMC4);
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break;
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case 5:
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val = mfpmr(PMRN_PMC5);
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break;
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default:
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printk(KERN_ERR "oops trying to read PMC%d\n", idx);
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val = 0;
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}
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return val;
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}
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/*
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* Write one PMC.
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*/
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static void write_pmc(int idx, unsigned long val)
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{
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switch (idx) {
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case 0:
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mtpmr(PMRN_PMC0, val);
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break;
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case 1:
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mtpmr(PMRN_PMC1, val);
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break;
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case 2:
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mtpmr(PMRN_PMC2, val);
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break;
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case 3:
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mtpmr(PMRN_PMC3, val);
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break;
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case 4:
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mtpmr(PMRN_PMC4, val);
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break;
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case 5:
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mtpmr(PMRN_PMC5, val);
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break;
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default:
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printk(KERN_ERR "oops trying to write PMC%d\n", idx);
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}
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isync();
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}
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/*
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* Write one local control A register
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*/
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static void write_pmlca(int idx, unsigned long val)
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{
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switch (idx) {
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case 0:
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mtpmr(PMRN_PMLCA0, val);
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break;
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case 1:
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mtpmr(PMRN_PMLCA1, val);
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break;
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case 2:
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mtpmr(PMRN_PMLCA2, val);
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break;
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case 3:
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mtpmr(PMRN_PMLCA3, val);
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break;
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case 4:
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mtpmr(PMRN_PMLCA4, val);
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break;
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case 5:
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mtpmr(PMRN_PMLCA5, val);
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break;
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default:
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printk(KERN_ERR "oops trying to write PMLCA%d\n", idx);
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}
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isync();
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}
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/*
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* Write one local control B register
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*/
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static void write_pmlcb(int idx, unsigned long val)
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{
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switch (idx) {
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case 0:
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mtpmr(PMRN_PMLCB0, val);
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break;
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case 1:
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mtpmr(PMRN_PMLCB1, val);
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break;
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case 2:
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mtpmr(PMRN_PMLCB2, val);
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break;
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case 3:
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mtpmr(PMRN_PMLCB3, val);
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break;
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case 4:
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mtpmr(PMRN_PMLCB4, val);
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break;
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case 5:
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mtpmr(PMRN_PMLCB5, val);
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break;
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default:
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printk(KERN_ERR "oops trying to write PMLCB%d\n", idx);
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}
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isync();
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}
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static void fsl_emb_pmu_read(struct perf_event *event)
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{
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s64 val, delta, prev;
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if (event->hw.state & PERF_HES_STOPPED)
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return;
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/*
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* Performance monitor interrupts come even when interrupts
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* are soft-disabled, as long as interrupts are hard-enabled.
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* Therefore we treat them like NMIs.
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*/
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do {
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prev = local64_read(&event->hw.prev_count);
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barrier();
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val = read_pmc(event->hw.idx);
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} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
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/* The counters are only 32 bits wide */
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delta = (val - prev) & 0xfffffffful;
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local64_add(delta, &event->count);
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local64_sub(delta, &event->hw.period_left);
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}
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/*
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* Disable all events to prevent PMU interrupts and to allow
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* events to be added or removed.
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*/
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static void fsl_emb_pmu_disable(struct pmu *pmu)
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{
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struct cpu_hw_events *cpuhw;
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unsigned long flags;
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local_irq_save(flags);
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cpuhw = this_cpu_ptr(&cpu_hw_events);
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if (!cpuhw->disabled) {
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cpuhw->disabled = 1;
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/*
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* Check if we ever enabled the PMU on this cpu.
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*/
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if (!cpuhw->pmcs_enabled) {
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ppc_enable_pmcs();
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cpuhw->pmcs_enabled = 1;
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}
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if (atomic_read(&num_events)) {
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/*
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* Set the 'freeze all counters' bit, and disable
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* interrupts. The barrier is to make sure the
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* mtpmr has been executed and the PMU has frozen
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* the events before we return.
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*/
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mtpmr(PMRN_PMGC0, PMGC0_FAC);
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isync();
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}
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}
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local_irq_restore(flags);
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}
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/*
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* Re-enable all events if disable == 0.
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* If we were previously disabled and events were added, then
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* put the new config on the PMU.
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*/
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static void fsl_emb_pmu_enable(struct pmu *pmu)
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{
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struct cpu_hw_events *cpuhw;
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unsigned long flags;
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local_irq_save(flags);
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cpuhw = this_cpu_ptr(&cpu_hw_events);
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if (!cpuhw->disabled)
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goto out;
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cpuhw->disabled = 0;
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ppc_set_pmu_inuse(cpuhw->n_events != 0);
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if (cpuhw->n_events > 0) {
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mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
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isync();
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}
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out:
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local_irq_restore(flags);
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}
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static int collect_events(struct perf_event *group, int max_count,
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struct perf_event *ctrs[])
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{
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int n = 0;
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struct perf_event *event;
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if (!is_software_event(group)) {
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if (n >= max_count)
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return -1;
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ctrs[n] = group;
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n++;
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}
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for_each_sibling_event(event, group) {
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if (!is_software_event(event) &&
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event->state != PERF_EVENT_STATE_OFF) {
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if (n >= max_count)
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return -1;
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ctrs[n] = event;
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n++;
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}
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}
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return n;
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}
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/* context locked on entry */
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static int fsl_emb_pmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuhw;
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int ret = -EAGAIN;
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int num_counters = ppmu->n_counter;
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u64 val;
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int i;
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perf_pmu_disable(event->pmu);
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cpuhw = &get_cpu_var(cpu_hw_events);
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if (event->hw.config & FSL_EMB_EVENT_RESTRICTED)
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num_counters = ppmu->n_restricted;
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/*
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* Allocate counters from top-down, so that restricted-capable
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* counters are kept free as long as possible.
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*/
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for (i = num_counters - 1; i >= 0; i--) {
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if (cpuhw->event[i])
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continue;
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break;
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}
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if (i < 0)
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goto out;
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event->hw.idx = i;
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cpuhw->event[i] = event;
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++cpuhw->n_events;
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val = 0;
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if (event->hw.sample_period) {
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s64 left = local64_read(&event->hw.period_left);
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if (left < 0x80000000L)
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val = 0x80000000L - left;
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}
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local64_set(&event->hw.prev_count, val);
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if (unlikely(!(flags & PERF_EF_START))) {
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event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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val = 0;
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} else {
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event->hw.state &= ~(PERF_HES_STOPPED | PERF_HES_UPTODATE);
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}
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write_pmc(i, val);
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perf_event_update_userpage(event);
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write_pmlcb(i, event->hw.config >> 32);
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write_pmlca(i, event->hw.config_base);
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ret = 0;
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out:
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put_cpu_var(cpu_hw_events);
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perf_pmu_enable(event->pmu);
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return ret;
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}
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/* context locked on entry */
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static void fsl_emb_pmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuhw;
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int i = event->hw.idx;
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perf_pmu_disable(event->pmu);
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if (i < 0)
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goto out;
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fsl_emb_pmu_read(event);
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cpuhw = &get_cpu_var(cpu_hw_events);
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WARN_ON(event != cpuhw->event[event->hw.idx]);
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write_pmlca(i, 0);
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write_pmlcb(i, 0);
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write_pmc(i, 0);
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cpuhw->event[i] = NULL;
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event->hw.idx = -1;
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/*
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* TODO: if at least one restricted event exists, and we
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* just freed up a non-restricted-capable counter, and
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* there is a restricted-capable counter occupied by
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* a non-restricted event, migrate that event to the
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* vacated counter.
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*/
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cpuhw->n_events--;
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out:
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perf_pmu_enable(event->pmu);
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put_cpu_var(cpu_hw_events);
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}
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static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags)
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{
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unsigned long flags;
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unsigned long val;
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s64 left;
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if (event->hw.idx < 0 || !event->hw.sample_period)
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return;
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if (!(event->hw.state & PERF_HES_STOPPED))
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return;
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if (ef_flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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local_irq_save(flags);
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perf_pmu_disable(event->pmu);
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event->hw.state = 0;
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left = local64_read(&event->hw.period_left);
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val = 0;
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if (left < 0x80000000L)
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val = 0x80000000L - left;
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write_pmc(event->hw.idx, val);
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perf_event_update_userpage(event);
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|
|
perf_pmu_enable(event->pmu);
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void fsl_emb_pmu_stop(struct perf_event *event, int ef_flags)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
if (event->hw.idx < 0 || !event->hw.sample_period)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (event->hw.state & PERF_HES_STOPPED)
|
||
|
|
return;
|
||
|
|
|
||
|
|
local_irq_save(flags);
|
||
|
|
perf_pmu_disable(event->pmu);
|
||
|
|
|
||
|
|
fsl_emb_pmu_read(event);
|
||
|
|
event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
||
|
|
write_pmc(event->hw.idx, 0);
|
||
|
|
|
||
|
|
perf_event_update_userpage(event);
|
||
|
|
perf_pmu_enable(event->pmu);
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Release the PMU if this is the last perf_event.
|
||
|
|
*/
|
||
|
|
static void hw_perf_event_destroy(struct perf_event *event)
|
||
|
|
{
|
||
|
|
if (!atomic_add_unless(&num_events, -1, 1)) {
|
||
|
|
mutex_lock(&pmc_reserve_mutex);
|
||
|
|
if (atomic_dec_return(&num_events) == 0)
|
||
|
|
release_pmc_hardware();
|
||
|
|
mutex_unlock(&pmc_reserve_mutex);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Translate a generic cache event_id config to a raw event_id code.
|
||
|
|
*/
|
||
|
|
static int hw_perf_cache_event(u64 config, u64 *eventp)
|
||
|
|
{
|
||
|
|
unsigned long type, op, result;
|
||
|
|
int ev;
|
||
|
|
|
||
|
|
if (!ppmu->cache_events)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
/* unpack config */
|
||
|
|
type = config & 0xff;
|
||
|
|
op = (config >> 8) & 0xff;
|
||
|
|
result = (config >> 16) & 0xff;
|
||
|
|
|
||
|
|
if (type >= PERF_COUNT_HW_CACHE_MAX ||
|
||
|
|
op >= PERF_COUNT_HW_CACHE_OP_MAX ||
|
||
|
|
result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
ev = (*ppmu->cache_events)[type][op][result];
|
||
|
|
if (ev == 0)
|
||
|
|
return -EOPNOTSUPP;
|
||
|
|
if (ev == -1)
|
||
|
|
return -EINVAL;
|
||
|
|
*eventp = ev;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int fsl_emb_pmu_event_init(struct perf_event *event)
|
||
|
|
{
|
||
|
|
u64 ev;
|
||
|
|
struct perf_event *events[MAX_HWEVENTS];
|
||
|
|
int n;
|
||
|
|
int err;
|
||
|
|
int num_restricted;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (ppmu->n_counter > MAX_HWEVENTS) {
|
||
|
|
WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n",
|
||
|
|
ppmu->n_counter, MAX_HWEVENTS);
|
||
|
|
ppmu->n_counter = MAX_HWEVENTS;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (event->attr.type) {
|
||
|
|
case PERF_TYPE_HARDWARE:
|
||
|
|
ev = event->attr.config;
|
||
|
|
if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
|
||
|
|
return -EOPNOTSUPP;
|
||
|
|
ev = ppmu->generic_events[ev];
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PERF_TYPE_HW_CACHE:
|
||
|
|
err = hw_perf_cache_event(event->attr.config, &ev);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PERF_TYPE_RAW:
|
||
|
|
ev = event->attr.config;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return -ENOENT;
|
||
|
|
}
|
||
|
|
|
||
|
|
event->hw.config = ppmu->xlate_event(ev);
|
||
|
|
if (!(event->hw.config & FSL_EMB_EVENT_VALID))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If this is in a group, check if it can go on with all the
|
||
|
|
* other hardware events in the group. We assume the event
|
||
|
|
* hasn't been linked into its leader's sibling list at this point.
|
||
|
|
*/
|
||
|
|
n = 0;
|
||
|
|
if (event->group_leader != event) {
|
||
|
|
n = collect_events(event->group_leader,
|
||
|
|
ppmu->n_counter - 1, events);
|
||
|
|
if (n < 0)
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) {
|
||
|
|
num_restricted = 0;
|
||
|
|
for (i = 0; i < n; i++) {
|
||
|
|
if (events[i]->hw.config & FSL_EMB_EVENT_RESTRICTED)
|
||
|
|
num_restricted++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (num_restricted >= ppmu->n_restricted)
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
event->hw.idx = -1;
|
||
|
|
|
||
|
|
event->hw.config_base = PMLCA_CE | PMLCA_FCM1 |
|
||
|
|
(u32)((ev << 16) & PMLCA_EVENT_MASK);
|
||
|
|
|
||
|
|
if (event->attr.exclude_user)
|
||
|
|
event->hw.config_base |= PMLCA_FCU;
|
||
|
|
if (event->attr.exclude_kernel)
|
||
|
|
event->hw.config_base |= PMLCA_FCS;
|
||
|
|
if (event->attr.exclude_idle)
|
||
|
|
return -ENOTSUPP;
|
||
|
|
|
||
|
|
event->hw.last_period = event->hw.sample_period;
|
||
|
|
local64_set(&event->hw.period_left, event->hw.last_period);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* See if we need to reserve the PMU.
|
||
|
|
* If no events are currently in use, then we have to take a
|
||
|
|
* mutex to ensure that we don't race with another task doing
|
||
|
|
* reserve_pmc_hardware or release_pmc_hardware.
|
||
|
|
*/
|
||
|
|
err = 0;
|
||
|
|
if (!atomic_inc_not_zero(&num_events)) {
|
||
|
|
mutex_lock(&pmc_reserve_mutex);
|
||
|
|
if (atomic_read(&num_events) == 0 &&
|
||
|
|
reserve_pmc_hardware(perf_event_interrupt))
|
||
|
|
err = -EBUSY;
|
||
|
|
else
|
||
|
|
atomic_inc(&num_events);
|
||
|
|
mutex_unlock(&pmc_reserve_mutex);
|
||
|
|
|
||
|
|
mtpmr(PMRN_PMGC0, PMGC0_FAC);
|
||
|
|
isync();
|
||
|
|
}
|
||
|
|
event->destroy = hw_perf_event_destroy;
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pmu fsl_emb_pmu = {
|
||
|
|
.pmu_enable = fsl_emb_pmu_enable,
|
||
|
|
.pmu_disable = fsl_emb_pmu_disable,
|
||
|
|
.event_init = fsl_emb_pmu_event_init,
|
||
|
|
.add = fsl_emb_pmu_add,
|
||
|
|
.del = fsl_emb_pmu_del,
|
||
|
|
.start = fsl_emb_pmu_start,
|
||
|
|
.stop = fsl_emb_pmu_stop,
|
||
|
|
.read = fsl_emb_pmu_read,
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* A counter has overflowed; update its count and record
|
||
|
|
* things if requested. Note that interrupts are hard-disabled
|
||
|
|
* here so there is no possibility of being interrupted.
|
||
|
|
*/
|
||
|
|
static void record_and_restart(struct perf_event *event, unsigned long val,
|
||
|
|
struct pt_regs *regs)
|
||
|
|
{
|
||
|
|
u64 period = event->hw.sample_period;
|
||
|
|
s64 prev, delta, left;
|
||
|
|
int record = 0;
|
||
|
|
|
||
|
|
if (event->hw.state & PERF_HES_STOPPED) {
|
||
|
|
write_pmc(event->hw.idx, 0);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* we don't have to worry about interrupts here */
|
||
|
|
prev = local64_read(&event->hw.prev_count);
|
||
|
|
delta = (val - prev) & 0xfffffffful;
|
||
|
|
local64_add(delta, &event->count);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* See if the total period for this event has expired,
|
||
|
|
* and update for the next period.
|
||
|
|
*/
|
||
|
|
val = 0;
|
||
|
|
left = local64_read(&event->hw.period_left) - delta;
|
||
|
|
if (period) {
|
||
|
|
if (left <= 0) {
|
||
|
|
left += period;
|
||
|
|
if (left <= 0)
|
||
|
|
left = period;
|
||
|
|
record = 1;
|
||
|
|
event->hw.last_period = event->hw.sample_period;
|
||
|
|
}
|
||
|
|
if (left < 0x80000000LL)
|
||
|
|
val = 0x80000000LL - left;
|
||
|
|
}
|
||
|
|
|
||
|
|
write_pmc(event->hw.idx, val);
|
||
|
|
local64_set(&event->hw.prev_count, val);
|
||
|
|
local64_set(&event->hw.period_left, left);
|
||
|
|
perf_event_update_userpage(event);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Finally record data if requested.
|
||
|
|
*/
|
||
|
|
if (record) {
|
||
|
|
struct perf_sample_data data;
|
||
|
|
|
||
|
|
perf_sample_data_init(&data, 0, event->hw.last_period);
|
||
|
|
|
||
|
|
if (perf_event_overflow(event, &data, regs))
|
||
|
|
fsl_emb_pmu_stop(event, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void perf_event_interrupt(struct pt_regs *regs)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
||
|
|
struct perf_event *event;
|
||
|
|
unsigned long val;
|
||
|
|
int found = 0;
|
||
|
|
|
||
|
|
for (i = 0; i < ppmu->n_counter; ++i) {
|
||
|
|
event = cpuhw->event[i];
|
||
|
|
|
||
|
|
val = read_pmc(i);
|
||
|
|
if ((int)val < 0) {
|
||
|
|
if (event) {
|
||
|
|
/* event has overflowed */
|
||
|
|
found = 1;
|
||
|
|
record_and_restart(event, val, regs);
|
||
|
|
} else {
|
||
|
|
/*
|
||
|
|
* Disabled counter is negative,
|
||
|
|
* reset it just in case.
|
||
|
|
*/
|
||
|
|
write_pmc(i, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* PMM will keep counters frozen until we return from the interrupt. */
|
||
|
|
mtmsr(mfmsr() | MSR_PMM);
|
||
|
|
mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
|
||
|
|
isync();
|
||
|
|
}
|
||
|
|
|
||
|
|
void hw_perf_event_setup(int cpu)
|
||
|
|
{
|
||
|
|
struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
|
||
|
|
|
||
|
|
memset(cpuhw, 0, sizeof(*cpuhw));
|
||
|
|
}
|
||
|
|
|
||
|
|
int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
|
||
|
|
{
|
||
|
|
if (ppmu)
|
||
|
|
return -EBUSY; /* something's already registered */
|
||
|
|
|
||
|
|
ppmu = pmu;
|
||
|
|
pr_info("%s performance monitor hardware support registered\n",
|
||
|
|
pmu->name);
|
||
|
|
|
||
|
|
perf_pmu_register(&fsl_emb_pmu, "cpu", PERF_TYPE_RAW);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|