512 lines
11 KiB
C
512 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright IBM Corp. 2008
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/disassemble.h>
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#include "booke.h"
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#define OP_19_XOP_RFI 50
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#define OP_19_XOP_RFCI 51
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#define OP_19_XOP_RFDI 39
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#define OP_31_XOP_MFMSR 83
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#define OP_31_XOP_WRTEE 131
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#define OP_31_XOP_MTMSR 146
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#define OP_31_XOP_WRTEEI 163
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static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
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kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
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}
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static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.regs.nip = vcpu->arch.dsrr0;
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kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
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}
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static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.regs.nip = vcpu->arch.csrr0;
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kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
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}
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int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
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unsigned int inst, int *advance)
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{
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int emulated = EMULATE_DONE;
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int rs = get_rs(inst);
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int rt = get_rt(inst);
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switch (get_op(inst)) {
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case 19:
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switch (get_xop(inst)) {
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case OP_19_XOP_RFI:
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kvmppc_emul_rfi(vcpu);
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kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
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*advance = 0;
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break;
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case OP_19_XOP_RFCI:
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kvmppc_emul_rfci(vcpu);
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kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
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*advance = 0;
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break;
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case OP_19_XOP_RFDI:
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kvmppc_emul_rfdi(vcpu);
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kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
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*advance = 0;
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break;
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default:
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emulated = EMULATE_FAIL;
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break;
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}
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break;
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case 31:
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switch (get_xop(inst)) {
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case OP_31_XOP_MFMSR:
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kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
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kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
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break;
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case OP_31_XOP_MTMSR:
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kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
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kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
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break;
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case OP_31_XOP_WRTEE:
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vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
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| (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
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kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
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break;
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case OP_31_XOP_WRTEEI:
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vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
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| (inst & MSR_EE);
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kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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return emulated;
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}
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/*
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* NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
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* Their backing store is in real registers, and these functions
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* will return the wrong result if called for them in another context
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* (such as debugging).
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*/
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int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
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{
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int emulated = EMULATE_DONE;
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bool debug_inst = false;
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switch (sprn) {
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case SPRN_DEAR:
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vcpu->arch.shared->dar = spr_val;
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break;
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case SPRN_ESR:
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vcpu->arch.shared->esr = spr_val;
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break;
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case SPRN_CSRR0:
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vcpu->arch.csrr0 = spr_val;
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break;
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case SPRN_CSRR1:
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vcpu->arch.csrr1 = spr_val;
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break;
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case SPRN_DSRR0:
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vcpu->arch.dsrr0 = spr_val;
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break;
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case SPRN_DSRR1:
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vcpu->arch.dsrr1 = spr_val;
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break;
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case SPRN_IAC1:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.iac1 = spr_val;
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break;
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case SPRN_IAC2:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.iac2 = spr_val;
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break;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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case SPRN_IAC3:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.iac3 = spr_val;
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break;
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case SPRN_IAC4:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.iac4 = spr_val;
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break;
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#endif
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case SPRN_DAC1:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.dac1 = spr_val;
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break;
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case SPRN_DAC2:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.dac2 = spr_val;
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break;
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case SPRN_DBCR0:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
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DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4 |
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DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
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vcpu->arch.dbg_reg.dbcr0 = spr_val;
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break;
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case SPRN_DBCR1:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.dbcr1 = spr_val;
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break;
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case SPRN_DBCR2:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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debug_inst = true;
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vcpu->arch.dbg_reg.dbcr2 = spr_val;
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break;
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case SPRN_DBSR:
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/*
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* If userspace is debugging guest then guest
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* can not access debug registers.
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*/
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if (vcpu->guest_debug)
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break;
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vcpu->arch.dbsr &= ~spr_val;
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if (!(vcpu->arch.dbsr & ~DBSR_IDE))
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kvmppc_core_dequeue_debug(vcpu);
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break;
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case SPRN_TSR:
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kvmppc_clr_tsr_bits(vcpu, spr_val);
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break;
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case SPRN_TCR:
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/*
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* WRC is a 2-bit field that is supposed to preserve its
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* value once written to non-zero.
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*/
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if (vcpu->arch.tcr & TCR_WRC_MASK) {
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spr_val &= ~TCR_WRC_MASK;
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spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
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}
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kvmppc_set_tcr(vcpu, spr_val);
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break;
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case SPRN_DECAR:
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vcpu->arch.decar = spr_val;
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break;
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/*
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* Note: SPRG4-7 are user-readable.
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* These values are loaded into the real SPRGs when resuming the
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* guest (PR-mode only).
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*/
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case SPRN_SPRG4:
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kvmppc_set_sprg4(vcpu, spr_val);
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break;
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case SPRN_SPRG5:
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kvmppc_set_sprg5(vcpu, spr_val);
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break;
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case SPRN_SPRG6:
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kvmppc_set_sprg6(vcpu, spr_val);
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break;
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case SPRN_SPRG7:
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kvmppc_set_sprg7(vcpu, spr_val);
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break;
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case SPRN_IVPR:
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vcpu->arch.ivpr = spr_val;
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#ifdef CONFIG_KVM_BOOKE_HV
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mtspr(SPRN_GIVPR, spr_val);
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#endif
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break;
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case SPRN_IVOR0:
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vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
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break;
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case SPRN_IVOR1:
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vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
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break;
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case SPRN_IVOR2:
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vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
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#ifdef CONFIG_KVM_BOOKE_HV
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mtspr(SPRN_GIVOR2, spr_val);
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#endif
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break;
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case SPRN_IVOR3:
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vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
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break;
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case SPRN_IVOR4:
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vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
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break;
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case SPRN_IVOR5:
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vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
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break;
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case SPRN_IVOR6:
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vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
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break;
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case SPRN_IVOR7:
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vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
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break;
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case SPRN_IVOR8:
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vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
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#ifdef CONFIG_KVM_BOOKE_HV
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mtspr(SPRN_GIVOR8, spr_val);
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#endif
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break;
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case SPRN_IVOR9:
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vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
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break;
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case SPRN_IVOR10:
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vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
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break;
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case SPRN_IVOR11:
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vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
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break;
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case SPRN_IVOR12:
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vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
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break;
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case SPRN_IVOR13:
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vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
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break;
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case SPRN_IVOR14:
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vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
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break;
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case SPRN_IVOR15:
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vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
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break;
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case SPRN_MCSR:
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vcpu->arch.mcsr &= ~spr_val;
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break;
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#if defined(CONFIG_64BIT)
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case SPRN_EPCR:
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kvmppc_set_epcr(vcpu, spr_val);
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#ifdef CONFIG_KVM_BOOKE_HV
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mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
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#endif
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break;
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#endif
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default:
|
||
|
|
emulated = EMULATE_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (debug_inst) {
|
||
|
|
current->thread.debug = vcpu->arch.dbg_reg;
|
||
|
|
switch_booke_debug_regs(&vcpu->arch.dbg_reg);
|
||
|
|
}
|
||
|
|
return emulated;
|
||
|
|
}
|
||
|
|
|
||
|
|
int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
|
||
|
|
{
|
||
|
|
int emulated = EMULATE_DONE;
|
||
|
|
|
||
|
|
switch (sprn) {
|
||
|
|
case SPRN_IVPR:
|
||
|
|
*spr_val = vcpu->arch.ivpr;
|
||
|
|
break;
|
||
|
|
case SPRN_DEAR:
|
||
|
|
*spr_val = vcpu->arch.shared->dar;
|
||
|
|
break;
|
||
|
|
case SPRN_ESR:
|
||
|
|
*spr_val = vcpu->arch.shared->esr;
|
||
|
|
break;
|
||
|
|
case SPRN_EPR:
|
||
|
|
*spr_val = vcpu->arch.epr;
|
||
|
|
break;
|
||
|
|
case SPRN_CSRR0:
|
||
|
|
*spr_val = vcpu->arch.csrr0;
|
||
|
|
break;
|
||
|
|
case SPRN_CSRR1:
|
||
|
|
*spr_val = vcpu->arch.csrr1;
|
||
|
|
break;
|
||
|
|
case SPRN_DSRR0:
|
||
|
|
*spr_val = vcpu->arch.dsrr0;
|
||
|
|
break;
|
||
|
|
case SPRN_DSRR1:
|
||
|
|
*spr_val = vcpu->arch.dsrr1;
|
||
|
|
break;
|
||
|
|
case SPRN_IAC1:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.iac1;
|
||
|
|
break;
|
||
|
|
case SPRN_IAC2:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.iac2;
|
||
|
|
break;
|
||
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
||
|
|
case SPRN_IAC3:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.iac3;
|
||
|
|
break;
|
||
|
|
case SPRN_IAC4:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.iac4;
|
||
|
|
break;
|
||
|
|
#endif
|
||
|
|
case SPRN_DAC1:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.dac1;
|
||
|
|
break;
|
||
|
|
case SPRN_DAC2:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.dac2;
|
||
|
|
break;
|
||
|
|
case SPRN_DBCR0:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.dbcr0;
|
||
|
|
if (vcpu->guest_debug)
|
||
|
|
*spr_val = *spr_val | DBCR0_EDM;
|
||
|
|
break;
|
||
|
|
case SPRN_DBCR1:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.dbcr1;
|
||
|
|
break;
|
||
|
|
case SPRN_DBCR2:
|
||
|
|
*spr_val = vcpu->arch.dbg_reg.dbcr2;
|
||
|
|
break;
|
||
|
|
case SPRN_DBSR:
|
||
|
|
*spr_val = vcpu->arch.dbsr;
|
||
|
|
break;
|
||
|
|
case SPRN_TSR:
|
||
|
|
*spr_val = vcpu->arch.tsr;
|
||
|
|
break;
|
||
|
|
case SPRN_TCR:
|
||
|
|
*spr_val = vcpu->arch.tcr;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SPRN_IVOR0:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR1:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR2:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR3:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR4:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR5:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR6:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR7:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR8:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR9:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR10:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR11:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR12:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR13:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR14:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
|
||
|
|
break;
|
||
|
|
case SPRN_IVOR15:
|
||
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
|
||
|
|
break;
|
||
|
|
case SPRN_MCSR:
|
||
|
|
*spr_val = vcpu->arch.mcsr;
|
||
|
|
break;
|
||
|
|
#if defined(CONFIG_64BIT)
|
||
|
|
case SPRN_EPCR:
|
||
|
|
*spr_val = vcpu->arch.epcr;
|
||
|
|
break;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
default:
|
||
|
|
emulated = EMULATE_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return emulated;
|
||
|
|
}
|