335 lines
11 KiB
C
335 lines
11 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Inline assembly cache operations.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_R4KCACHE_H
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#define _ASM_R4KCACHE_H
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#include <linux/stringify.h>
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#include <asm/asm.h>
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#include <asm/asm-eva.h>
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#include <asm/cacheops.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/mipsmtregs.h>
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#include <asm/mmzone.h>
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#include <asm/unroll.h>
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_icache)(void);
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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*
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* - The MIPS32 and MIPS64 specs permit an implementation to directly derive
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* the index bits from the virtual address. This breaks with tradition
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* set by the R4000. To keep unpleasant surprises from happening we pick
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* an address in KSEG0 / CKSEG0.
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* - We need a properly sign extended address for 64-bit code. To get away
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* without ifdefs we let the compiler do it by a type cast.
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*/
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#define INDEX_BASE CKSEG0
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#define _cache_op(insn, op, addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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" " insn("%0", "%1") " \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#define cache_op(op, addr) \
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_cache_op(kernel_cache, op, addr)
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Invalidate_I, addr);
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_D, addr);
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_SD, addr);
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}
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static inline void flush_icache_line(unsigned long addr)
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{
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switch (boot_cpu_type()) {
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case CPU_LOONGSON2EF:
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cache_op(Hit_Invalidate_I_Loongson2, addr);
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break;
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default:
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cache_op(Hit_Invalidate_I, addr);
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break;
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}
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}
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static inline void flush_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_D, addr);
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}
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static inline void invalidate_scache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_SD, addr);
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}
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static inline void flush_scache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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#ifdef CONFIG_EVA
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#define protected_cache_op(op, addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips0 \n" \
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" .set eva \n" \
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"1: cachee %1, (%2) \n" \
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"2: .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR_WD)" 1b, 3b \n" \
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" .previous" \
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#else
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#define protected_cache_op(op, addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"1: cache %1, (%2) \n" \
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"2: .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR_WD)" 1b, 3b \n" \
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" .previous" \
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#endif
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline int protected_flush_icache_line(unsigned long addr)
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{
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switch (boot_cpu_type()) {
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case CPU_LOONGSON2EF:
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return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
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default:
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return protected_cache_op(Hit_Invalidate_I, addr);
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}
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}
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/*
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* R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
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* cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penalty isn't overly hard.
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*/
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static inline int protected_writeback_dcache_line(unsigned long addr)
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{
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return protected_cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline int protected_writeback_scache_line(unsigned long addr)
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{
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return protected_cache_op(Hit_Writeback_Inv_SD, addr);
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}
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/*
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* This one is RM7000-specific
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*/
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static inline void invalidate_tcache_page(unsigned long addr)
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{
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cache_op(Page_Invalidate_T, addr);
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}
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#define cache_unroll(times, insn, op, addr, lsize) do { \
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int i = 0; \
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unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
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} while (0)
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
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static inline void extra##blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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unsigned long end = start + current_cpu_data.desc.waysize; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache_unroll(32, kernel_cache, indexop, \
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addr | ws, lsize); \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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do { \
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cache_unroll(32, kernel_cache, hitop, start, lsize); \
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start += lsize * 32; \
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} while (start < end); \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
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{ \
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unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
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unsigned long start = INDEX_BASE + (page & indexmask); \
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unsigned long end = start + PAGE_SIZE; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache_unroll(32, kernel_cache, indexop, \
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addr | ws, lsize); \
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}
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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do { \
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cache_unroll(32, user_cache, hitop, start, lsize); \
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start += lsize * 32; \
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} while (start < end); \
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}
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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16)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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32)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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64)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
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static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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while (1) { \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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}
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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protected_, loongson2_)
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
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/* blast_inv_dcache_range */
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__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
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__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
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/* Currently, this is very specific to Loongson-3 */
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#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_node(long node) \
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{ \
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unsigned long start = CAC_BASE | nid_to_addrbase(node); \
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unsigned long end = start + current_cpu_data.desc.waysize; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache_unroll(32, kernel_cache, indexop, \
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addr | ws, lsize); \
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}
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__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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#endif /* _ASM_R4KCACHE_H */
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