255 lines
5.4 KiB
C
255 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* otg.c - ChipIdea USB IP core OTG driver
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Author: Peter Chen
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*/
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/*
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* This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
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* are also included.
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*/
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#include <linux/usb/otg.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/chipidea.h>
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#include "ci.h"
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#include "bits.h"
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#include "otg.h"
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#include "otg_fsm.h"
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/**
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* hw_read_otgsc returns otgsc register bits value.
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* @mask: bitfield mask
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*/
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u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
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{
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struct ci_hdrc_cable *cable;
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u32 val = hw_read(ci, OP_OTGSC, mask);
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/*
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* If using extcon framework for VBUS and/or ID signal
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* detection overwrite OTGSC register value
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*/
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cable = &ci->platdata->vbus_extcon;
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if (!IS_ERR(cable->edev)) {
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if (cable->changed)
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val |= OTGSC_BSVIS;
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else
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val &= ~OTGSC_BSVIS;
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if (cable->connected)
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val |= OTGSC_BSV;
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else
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val &= ~OTGSC_BSV;
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if (cable->enabled)
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val |= OTGSC_BSVIE;
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else
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val &= ~OTGSC_BSVIE;
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}
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cable = &ci->platdata->id_extcon;
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if (!IS_ERR(cable->edev)) {
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if (cable->changed)
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val |= OTGSC_IDIS;
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else
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val &= ~OTGSC_IDIS;
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if (cable->connected)
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val &= ~OTGSC_ID; /* host */
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else
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val |= OTGSC_ID; /* device */
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if (cable->enabled)
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val |= OTGSC_IDIE;
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else
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val &= ~OTGSC_IDIE;
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}
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return val & mask;
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}
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/**
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* hw_write_otgsc updates target bits of OTGSC register.
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* @mask: bitfield mask
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* @data: to be written
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*/
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void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
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{
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struct ci_hdrc_cable *cable;
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cable = &ci->platdata->vbus_extcon;
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if (!IS_ERR(cable->edev)) {
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if (data & mask & OTGSC_BSVIS)
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cable->changed = false;
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/* Don't enable vbus interrupt if using external notifier */
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if (data & mask & OTGSC_BSVIE) {
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cable->enabled = true;
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data &= ~OTGSC_BSVIE;
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} else if (mask & OTGSC_BSVIE) {
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cable->enabled = false;
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}
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}
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cable = &ci->platdata->id_extcon;
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if (!IS_ERR(cable->edev)) {
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if (data & mask & OTGSC_IDIS)
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cable->changed = false;
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/* Don't enable id interrupt if using external notifier */
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if (data & mask & OTGSC_IDIE) {
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cable->enabled = true;
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data &= ~OTGSC_IDIE;
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} else if (mask & OTGSC_IDIE) {
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cable->enabled = false;
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}
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}
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hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
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}
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/**
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* ci_otg_role - pick role based on ID pin state
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* @ci: the controller
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*/
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enum ci_role ci_otg_role(struct ci_hdrc *ci)
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{
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enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
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? CI_ROLE_GADGET
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: CI_ROLE_HOST;
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return role;
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}
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void ci_handle_vbus_change(struct ci_hdrc *ci)
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{
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if (!ci->is_otg)
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return;
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if (hw_read_otgsc(ci, OTGSC_BSV) && !ci->vbus_active)
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usb_gadget_vbus_connect(&ci->gadget);
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else if (!hw_read_otgsc(ci, OTGSC_BSV) && ci->vbus_active)
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usb_gadget_vbus_disconnect(&ci->gadget);
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}
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/**
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* When we switch to device mode, the vbus value should be lower
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* than OTGSC_BSV before connecting to host.
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*
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* @ci: the controller
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*
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* This function returns an error code if timeout
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*/
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static int hw_wait_vbus_lower_bsv(struct ci_hdrc *ci)
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{
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unsigned long elapse = jiffies + msecs_to_jiffies(5000);
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u32 mask = OTGSC_BSV;
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while (hw_read_otgsc(ci, mask)) {
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if (time_after(jiffies, elapse)) {
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dev_err(ci->dev, "timeout waiting for %08x in OTGSC\n",
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mask);
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return -ETIMEDOUT;
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}
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msleep(20);
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}
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return 0;
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}
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static void ci_handle_id_switch(struct ci_hdrc *ci)
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{
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enum ci_role role = ci_otg_role(ci);
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if (role != ci->role) {
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dev_dbg(ci->dev, "switching from %s to %s\n",
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ci_role(ci)->name, ci->roles[role]->name);
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ci_role_stop(ci);
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if (role == CI_ROLE_GADGET &&
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IS_ERR(ci->platdata->vbus_extcon.edev))
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/*
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* Wait vbus lower than OTGSC_BSV before connecting
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* to host. If connecting status is from an external
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* connector instead of register, we don't need to
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* care vbus on the board, since it will not affect
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* external connector status.
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*/
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hw_wait_vbus_lower_bsv(ci);
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ci_role_start(ci, role);
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/* vbus change may have already occurred */
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if (role == CI_ROLE_GADGET)
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ci_handle_vbus_change(ci);
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}
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}
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/**
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* ci_otg_work - perform otg (vbus/id) event handle
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* @work: work struct
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*/
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static void ci_otg_work(struct work_struct *work)
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{
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struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
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if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) {
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enable_irq(ci->irq);
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return;
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}
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pm_runtime_get_sync(ci->dev);
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if (ci->id_event) {
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ci->id_event = false;
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ci_handle_id_switch(ci);
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} else if (ci->b_sess_valid_event) {
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ci->b_sess_valid_event = false;
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ci_handle_vbus_change(ci);
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} else
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dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
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pm_runtime_put_sync(ci->dev);
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enable_irq(ci->irq);
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}
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/**
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* ci_hdrc_otg_init - initialize otg struct
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* ci: the controller
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*/
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int ci_hdrc_otg_init(struct ci_hdrc *ci)
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{
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INIT_WORK(&ci->work, ci_otg_work);
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ci->wq = create_freezable_workqueue("ci_otg");
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if (!ci->wq) {
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dev_err(ci->dev, "can't create workqueue\n");
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return -ENODEV;
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}
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if (ci_otg_is_fsm_mode(ci))
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return ci_hdrc_otg_fsm_init(ci);
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return 0;
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}
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/**
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* ci_hdrc_otg_destroy - destroy otg struct
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* ci: the controller
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*/
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void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
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{
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if (ci->wq) {
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flush_workqueue(ci->wq);
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destroy_workqueue(ci->wq);
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}
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/* Disable all OTG irq and clear status */
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hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
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OTGSC_INT_STATUS_BITS);
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if (ci_otg_is_fsm_mode(ci))
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ci_hdrc_otg_fsm_remove(ci);
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}
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