454 lines
12 KiB
C
454 lines
12 KiB
C
/*
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* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
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*
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* Copyright (c) 2010, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
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#define TEGRA_RTC_REG_BUSY 0x004
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#define TEGRA_RTC_REG_SECONDS 0x008
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/* when msec is read, the seconds are buffered into shadow seconds. */
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#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
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#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
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#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
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#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
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#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
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#define TEGRA_RTC_REG_INTR_MASK 0x028
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/* write 1 bits to clear status bits */
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#define TEGRA_RTC_REG_INTR_STATUS 0x02c
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/* bits in INTR_MASK */
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#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
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#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
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#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
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#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
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#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
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/* bits in INTR_STATUS */
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#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
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#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
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#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
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#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
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#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
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struct tegra_rtc_info {
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struct platform_device *pdev;
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struct rtc_device *rtc_dev;
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void __iomem *rtc_base; /* NULL if not initialized. */
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struct clk *clk;
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int tegra_rtc_irq; /* alarm and periodic irq */
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spinlock_t tegra_rtc_lock;
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};
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/* RTC hardware is busy when it is updating its values over AHB once
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* every eight 32kHz clocks (~250uS).
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* outside of these updates the CPU is free to write.
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* CPU is always free to read.
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*/
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static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
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{
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return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
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}
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/* Wait for hardware to be ready for writing.
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* This function tries to maximize the amount of time before the next update.
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* It does this by waiting for the RTC to become busy with its periodic update,
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* then returning once the RTC first becomes not busy.
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* This periodic update (where the seconds and milliseconds are copied to the
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* AHB side) occurs every eight 32kHz clocks (~250uS).
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* The behavior of this function allows us to make some assumptions without
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* introducing a race, because 250uS is plenty of time to read/write a value.
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*/
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static int tegra_rtc_wait_while_busy(struct device *dev)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
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/* first wait for the RTC to become busy. this is when it
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* posts its updated seconds+msec registers to AHB side. */
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while (tegra_rtc_check_busy(info)) {
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if (!retries--)
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goto retry_failed;
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udelay(1);
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}
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/* now we have about 250 us to manipulate registers */
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return 0;
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retry_failed:
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dev_err(dev, "write failed:retry count exceeded.\n");
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return -ETIMEDOUT;
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}
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static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned long sec, msec;
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unsigned long sl_irq_flags;
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/* RTC hardware copies seconds to shadow seconds when a read
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* of milliseconds occurs. use a lock to keep other threads out. */
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spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
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msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
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sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
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spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
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rtc_time_to_tm(sec, tm);
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dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
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sec,
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tm->tm_mon + 1,
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tm->tm_mday,
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tm->tm_year + 1900,
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tm->tm_hour,
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tm->tm_min,
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tm->tm_sec
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);
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return 0;
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}
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static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned long sec;
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int ret;
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/* convert tm to seconds. */
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ret = rtc_valid_tm(tm);
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if (ret)
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return ret;
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rtc_tm_to_time(tm, &sec);
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dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
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sec,
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tm->tm_mon+1,
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tm->tm_mday,
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tm->tm_year+1900,
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tm->tm_hour,
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tm->tm_min,
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tm->tm_sec
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);
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/* seconds only written if wait succeeded. */
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ret = tegra_rtc_wait_while_busy(dev);
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if (!ret)
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writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
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dev_vdbg(dev, "time read back as %d\n",
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readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
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return ret;
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}
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static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned long sec;
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unsigned tmp;
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sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
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if (sec == 0) {
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/* alarm is disabled. */
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alarm->enabled = 0;
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} else {
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/* alarm is enabled. */
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alarm->enabled = 1;
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rtc_time_to_tm(sec, &alarm->time);
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}
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tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
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alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
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return 0;
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}
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static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned status;
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unsigned long sl_irq_flags;
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tegra_rtc_wait_while_busy(dev);
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spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
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/* read the original value, and OR in the flag. */
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status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
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if (enabled)
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status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
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else
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status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
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writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
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spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
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return 0;
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}
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static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned long sec;
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if (alarm->enabled)
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rtc_tm_to_time(&alarm->time, &sec);
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else
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sec = 0;
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tegra_rtc_wait_while_busy(dev);
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writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
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dev_vdbg(dev, "alarm read back as %d\n",
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readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
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/* if successfully written and alarm is enabled ... */
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if (sec) {
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tegra_rtc_alarm_irq_enable(dev, 1);
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dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
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sec,
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alarm->time.tm_mon+1,
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alarm->time.tm_mday,
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alarm->time.tm_year+1900,
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alarm->time.tm_hour,
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alarm->time.tm_min,
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alarm->time.tm_sec);
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} else {
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/* disable alarm if 0 or write error. */
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dev_vdbg(dev, "alarm disabled\n");
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tegra_rtc_alarm_irq_enable(dev, 0);
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}
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return 0;
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}
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static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
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{
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if (!dev || !dev->driver)
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return 0;
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seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
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return 0;
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}
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static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
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{
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struct device *dev = data;
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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unsigned long events = 0;
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unsigned status;
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unsigned long sl_irq_flags;
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status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
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if (status) {
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/* clear the interrupt masks and status on any irq. */
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tegra_rtc_wait_while_busy(dev);
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spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
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writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
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writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
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spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
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}
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/* check if Alarm */
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if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
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events |= RTC_IRQF | RTC_AF;
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/* check if Periodic */
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if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
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events |= RTC_IRQF | RTC_PF;
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rtc_update_irq(info->rtc_dev, 1, events);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops tegra_rtc_ops = {
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.read_time = tegra_rtc_read_time,
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.set_time = tegra_rtc_set_time,
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.read_alarm = tegra_rtc_read_alarm,
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.set_alarm = tegra_rtc_set_alarm,
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.proc = tegra_rtc_proc,
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.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
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};
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static const struct of_device_id tegra_rtc_dt_match[] = {
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{ .compatible = "nvidia,tegra20-rtc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
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static int __init tegra_rtc_probe(struct platform_device *pdev)
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{
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struct tegra_rtc_info *info;
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struct resource *res;
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int ret;
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info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
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GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(info->rtc_base))
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return PTR_ERR(info->rtc_base);
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info->tegra_rtc_irq = platform_get_irq(pdev, 0);
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if (info->tegra_rtc_irq <= 0)
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return -EBUSY;
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info->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(info->clk))
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return PTR_ERR(info->clk);
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ret = clk_prepare_enable(info->clk);
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if (ret < 0)
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return ret;
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/* set context info. */
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info->pdev = pdev;
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spin_lock_init(&info->tegra_rtc_lock);
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platform_set_drvdata(pdev, info);
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/* clear out the hardware. */
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writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
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writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
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writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
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device_init_wakeup(&pdev->dev, 1);
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info->rtc_dev = devm_rtc_device_register(&pdev->dev,
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dev_name(&pdev->dev), &tegra_rtc_ops,
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THIS_MODULE);
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if (IS_ERR(info->rtc_dev)) {
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ret = PTR_ERR(info->rtc_dev);
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dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
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ret);
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goto disable_clk;
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}
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ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
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tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
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dev_name(&pdev->dev), &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Unable to request interrupt for device (err=%d).\n",
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ret);
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goto disable_clk;
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}
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dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
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return 0;
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disable_clk:
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clk_disable_unprepare(info->clk);
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return ret;
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}
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static int tegra_rtc_remove(struct platform_device *pdev)
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{
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struct tegra_rtc_info *info = platform_get_drvdata(pdev);
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clk_disable_unprepare(info->clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_rtc_suspend(struct device *dev)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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tegra_rtc_wait_while_busy(dev);
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/* only use ALARM0 as a wake source. */
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writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
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writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
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info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
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dev_vdbg(dev, "alarm sec = %d\n",
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readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
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dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
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device_may_wakeup(dev), info->tegra_rtc_irq);
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/* leave the alarms on as a wake source. */
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if (device_may_wakeup(dev))
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enable_irq_wake(info->tegra_rtc_irq);
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return 0;
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}
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static int tegra_rtc_resume(struct device *dev)
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{
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struct tegra_rtc_info *info = dev_get_drvdata(dev);
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dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
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device_may_wakeup(dev));
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/* alarms were left on as a wake source, turn them off. */
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if (device_may_wakeup(dev))
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disable_irq_wake(info->tegra_rtc_irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
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static void tegra_rtc_shutdown(struct platform_device *pdev)
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{
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dev_vdbg(&pdev->dev, "disabling interrupts.\n");
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tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
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}
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MODULE_ALIAS("platform:tegra_rtc");
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static struct platform_driver tegra_rtc_driver = {
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.remove = tegra_rtc_remove,
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.shutdown = tegra_rtc_shutdown,
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.driver = {
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.name = "tegra_rtc",
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.of_match_table = tegra_rtc_dt_match,
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.pm = &tegra_rtc_pm_ops,
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},
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};
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module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
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MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
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MODULE_DESCRIPTION("driver for Tegra internal RTC");
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MODULE_LICENSE("GPL");
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