354 lines
8.3 KiB
C
354 lines
8.3 KiB
C
/*
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* Copyright 2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/types.h>
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#define DTE_NCO_LOW_TIME_REG 0x00
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#define DTE_NCO_TIME_REG 0x04
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#define DTE_NCO_OVERFLOW_REG 0x08
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#define DTE_NCO_INC_REG 0x0c
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#define DTE_NCO_SUM2_MASK 0xffffffff
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#define DTE_NCO_SUM2_SHIFT 4ULL
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#define DTE_NCO_SUM3_MASK 0xff
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#define DTE_NCO_SUM3_SHIFT 36ULL
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#define DTE_NCO_SUM3_WR_SHIFT 8
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#define DTE_NCO_TS_WRAP_MASK 0xfff
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#define DTE_NCO_TS_WRAP_LSHIFT 32
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#define DTE_NCO_INC_DEFAULT 0x80000000
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#define DTE_NUM_REGS_TO_RESTORE 4
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/* Full wrap around is 44bits in ns (~4.887 hrs) */
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#define DTE_WRAP_AROUND_NSEC_SHIFT 44
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/* 44 bits NCO */
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#define DTE_NCO_MAX_NS 0xFFFFFFFFFFFLL
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/* 125MHz with 3.29 reg cfg */
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#define DTE_PPB_ADJ(ppb) (u32)(div64_u64((((u64)abs(ppb) * BIT(28)) +\
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62500000ULL), 125000000ULL))
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/* ptp dte priv structure */
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struct ptp_dte {
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void __iomem *regs;
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struct ptp_clock *ptp_clk;
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struct ptp_clock_info caps;
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struct device *dev;
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u32 ts_ovf_last;
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u32 ts_wrap_cnt;
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spinlock_t lock;
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u32 reg_val[DTE_NUM_REGS_TO_RESTORE];
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};
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static void dte_write_nco(void __iomem *regs, s64 ns)
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{
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u32 sum2, sum3;
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sum2 = (u32)((ns >> DTE_NCO_SUM2_SHIFT) & DTE_NCO_SUM2_MASK);
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/* compensate for ignoring sum1 */
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if (sum2 != DTE_NCO_SUM2_MASK)
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sum2++;
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/* to write sum3, bits [15:8] needs to be written */
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sum3 = (u32)(((ns >> DTE_NCO_SUM3_SHIFT) & DTE_NCO_SUM3_MASK) <<
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DTE_NCO_SUM3_WR_SHIFT);
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writel(0, (regs + DTE_NCO_LOW_TIME_REG));
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writel(sum2, (regs + DTE_NCO_TIME_REG));
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writel(sum3, (regs + DTE_NCO_OVERFLOW_REG));
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}
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static s64 dte_read_nco(void __iomem *regs)
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{
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u32 sum2, sum3;
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s64 ns;
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/*
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* ignoring sum1 (4 bits) gives a 16ns resolution, which
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* works due to the async register read.
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*/
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sum3 = readl(regs + DTE_NCO_OVERFLOW_REG) & DTE_NCO_SUM3_MASK;
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sum2 = readl(regs + DTE_NCO_TIME_REG);
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ns = ((s64)sum3 << DTE_NCO_SUM3_SHIFT) |
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((s64)sum2 << DTE_NCO_SUM2_SHIFT);
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return ns;
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}
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static void dte_write_nco_delta(struct ptp_dte *ptp_dte, s64 delta)
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{
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s64 ns;
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ns = dte_read_nco(ptp_dte->regs);
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/* handle wraparound conditions */
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if ((delta < 0) && (abs(delta) > ns)) {
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if (ptp_dte->ts_wrap_cnt) {
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ns += DTE_NCO_MAX_NS + delta;
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ptp_dte->ts_wrap_cnt--;
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} else {
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ns = 0;
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}
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} else {
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ns += delta;
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if (ns > DTE_NCO_MAX_NS) {
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ptp_dte->ts_wrap_cnt++;
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ns -= DTE_NCO_MAX_NS;
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}
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}
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dte_write_nco(ptp_dte->regs, ns);
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ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) &
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DTE_NCO_TS_WRAP_MASK;
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}
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static s64 dte_read_nco_with_ovf(struct ptp_dte *ptp_dte)
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{
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u32 ts_ovf;
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s64 ns = 0;
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ns = dte_read_nco(ptp_dte->regs);
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/*Timestamp overflow: 8 LSB bits of sum3, 4 MSB bits of sum2 */
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ts_ovf = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & DTE_NCO_TS_WRAP_MASK;
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/* Check for wrap around */
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if (ts_ovf < ptp_dte->ts_ovf_last)
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ptp_dte->ts_wrap_cnt++;
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ptp_dte->ts_ovf_last = ts_ovf;
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/* adjust for wraparounds */
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ns += (s64)(BIT_ULL(DTE_WRAP_AROUND_NSEC_SHIFT) * ptp_dte->ts_wrap_cnt);
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return ns;
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}
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static int ptp_dte_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u32 nco_incr;
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unsigned long flags;
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struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
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if (abs(ppb) > ptp_dte->caps.max_adj) {
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dev_err(ptp_dte->dev, "ppb adj too big\n");
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return -EINVAL;
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}
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if (ppb < 0)
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nco_incr = DTE_NCO_INC_DEFAULT - DTE_PPB_ADJ(ppb);
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else
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nco_incr = DTE_NCO_INC_DEFAULT + DTE_PPB_ADJ(ppb);
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spin_lock_irqsave(&ptp_dte->lock, flags);
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writel(nco_incr, ptp_dte->regs + DTE_NCO_INC_REG);
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spin_unlock_irqrestore(&ptp_dte->lock, flags);
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return 0;
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}
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static int ptp_dte_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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unsigned long flags;
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struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
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spin_lock_irqsave(&ptp_dte->lock, flags);
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dte_write_nco_delta(ptp_dte, delta);
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spin_unlock_irqrestore(&ptp_dte->lock, flags);
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return 0;
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}
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static int ptp_dte_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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unsigned long flags;
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struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
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spin_lock_irqsave(&ptp_dte->lock, flags);
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*ts = ns_to_timespec64(dte_read_nco_with_ovf(ptp_dte));
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spin_unlock_irqrestore(&ptp_dte->lock, flags);
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return 0;
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}
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static int ptp_dte_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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unsigned long flags;
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struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
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spin_lock_irqsave(&ptp_dte->lock, flags);
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/* Disable nco increment */
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writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
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dte_write_nco(ptp_dte->regs, timespec64_to_ns(ts));
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/* reset overflow and wrap counter */
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ptp_dte->ts_ovf_last = 0;
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ptp_dte->ts_wrap_cnt = 0;
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/* Enable nco increment */
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writel(DTE_NCO_INC_DEFAULT, ptp_dte->regs + DTE_NCO_INC_REG);
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spin_unlock_irqrestore(&ptp_dte->lock, flags);
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return 0;
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}
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static int ptp_dte_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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return -EOPNOTSUPP;
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}
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static const struct ptp_clock_info ptp_dte_caps = {
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.owner = THIS_MODULE,
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.name = "DTE PTP timer",
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.max_adj = 50000000,
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.n_ext_ts = 0,
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.n_pins = 0,
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.pps = 0,
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.adjfreq = ptp_dte_adjfreq,
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.adjtime = ptp_dte_adjtime,
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.gettime64 = ptp_dte_gettime,
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.settime64 = ptp_dte_settime,
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.enable = ptp_dte_enable,
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};
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static int ptp_dte_probe(struct platform_device *pdev)
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{
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struct ptp_dte *ptp_dte;
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struct device *dev = &pdev->dev;
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struct resource *res;
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ptp_dte = devm_kzalloc(dev, sizeof(struct ptp_dte), GFP_KERNEL);
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if (!ptp_dte)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ptp_dte->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(ptp_dte->regs)) {
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dev_err(dev,
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"%s: io remap failed\n", __func__);
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return PTR_ERR(ptp_dte->regs);
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}
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spin_lock_init(&ptp_dte->lock);
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ptp_dte->dev = dev;
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ptp_dte->caps = ptp_dte_caps;
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ptp_dte->ptp_clk = ptp_clock_register(&ptp_dte->caps, &pdev->dev);
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if (IS_ERR(ptp_dte->ptp_clk)) {
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dev_err(dev,
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"%s: Failed to register ptp clock\n", __func__);
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return PTR_ERR(ptp_dte->ptp_clk);
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}
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platform_set_drvdata(pdev, ptp_dte);
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dev_info(dev, "ptp clk probe done\n");
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return 0;
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}
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static int ptp_dte_remove(struct platform_device *pdev)
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{
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struct ptp_dte *ptp_dte = platform_get_drvdata(pdev);
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u8 i;
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ptp_clock_unregister(ptp_dte->ptp_clk);
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for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++)
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writel(0, ptp_dte->regs + (i * sizeof(u32)));
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ptp_dte_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct ptp_dte *ptp_dte = platform_get_drvdata(pdev);
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u8 i;
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for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) {
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ptp_dte->reg_val[i] =
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readl(ptp_dte->regs + (i * sizeof(u32)));
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}
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/* disable the nco */
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writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
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return 0;
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}
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static int ptp_dte_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct ptp_dte *ptp_dte = platform_get_drvdata(pdev);
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u8 i;
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for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) {
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if ((i * sizeof(u32)) != DTE_NCO_OVERFLOW_REG)
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writel(ptp_dte->reg_val[i],
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(ptp_dte->regs + (i * sizeof(u32))));
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else
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writel(((ptp_dte->reg_val[i] &
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DTE_NCO_SUM3_MASK) << DTE_NCO_SUM3_WR_SHIFT),
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(ptp_dte->regs + (i * sizeof(u32))));
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}
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return 0;
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}
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static const struct dev_pm_ops ptp_dte_pm_ops = {
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.suspend = ptp_dte_suspend,
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.resume = ptp_dte_resume
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};
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#define PTP_DTE_PM_OPS (&ptp_dte_pm_ops)
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#else
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#define PTP_DTE_PM_OPS NULL
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#endif
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static const struct of_device_id ptp_dte_of_match[] = {
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{ .compatible = "brcm,ptp-dte", },
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{},
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};
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MODULE_DEVICE_TABLE(of, ptp_dte_of_match);
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static struct platform_driver ptp_dte_driver = {
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.driver = {
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.name = "ptp-dte",
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.pm = PTP_DTE_PM_OPS,
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.of_match_table = ptp_dte_of_match,
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},
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.probe = ptp_dte_probe,
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.remove = ptp_dte_remove,
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};
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module_platform_driver(ptp_dte_driver);
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver");
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MODULE_LICENSE("GPL v2");
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