801 lines
18 KiB
C
801 lines
18 KiB
C
/*
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* Pin Control and GPIO driver for SuperH Pin Function Controller.
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*
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* Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
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*
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2009 - 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "sh-pfc"
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#include <linux/psci.h>
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#include <linux/slab.h>
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#include "core.h"
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static int sh_pfc_map_resources(struct sh_pfc *pfc,
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struct platform_device *pdev)
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{
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unsigned int num_windows, num_irqs;
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struct sh_pfc_window *windows;
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unsigned int *irqs = NULL;
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struct resource *res;
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unsigned int i;
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int irq;
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/* Count the MEM and IRQ resources. */
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for (num_windows = 0;; num_windows++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
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if (!res)
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break;
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}
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for (num_irqs = 0;; num_irqs++) {
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irq = platform_get_irq(pdev, num_irqs);
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if (irq == -EPROBE_DEFER)
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return irq;
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if (irq < 0)
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break;
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}
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if (num_windows == 0)
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return -EINVAL;
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/* Allocate memory windows and IRQs arrays. */
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windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
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GFP_KERNEL);
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if (windows == NULL)
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return -ENOMEM;
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pfc->num_windows = num_windows;
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pfc->windows = windows;
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if (num_irqs) {
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irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
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GFP_KERNEL);
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if (irqs == NULL)
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return -ENOMEM;
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pfc->num_irqs = num_irqs;
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pfc->irqs = irqs;
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}
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/* Fill them. */
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for (i = 0; i < num_windows; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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windows->phys = res->start;
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windows->size = resource_size(res);
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windows->virt = devm_ioremap_resource(pfc->dev, res);
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if (IS_ERR(windows->virt))
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return -ENOMEM;
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windows++;
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}
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for (i = 0; i < num_irqs; i++)
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*irqs++ = platform_get_irq(pdev, i);
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return 0;
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}
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static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
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{
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struct sh_pfc_window *window;
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phys_addr_t address = reg;
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unsigned int i;
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/* scan through physical windows and convert address */
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for (i = 0; i < pfc->num_windows; i++) {
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window = pfc->windows + i;
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if (address < window->phys)
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continue;
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if (address >= (window->phys + window->size))
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continue;
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return window->virt + (address - window->phys);
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}
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BUG();
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return NULL;
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}
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
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{
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unsigned int offset;
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unsigned int i;
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for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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if (pin <= range->end)
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return pin >= range->start
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? offset + pin - range->start : -1;
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offset += range->end - range->start + 1;
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}
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return -EINVAL;
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}
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static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
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{
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if (enum_id < r->begin)
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return 0;
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if (enum_id > r->end)
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return 0;
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return 1;
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}
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u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
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{
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switch (reg_width) {
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case 8:
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return ioread8(mapped_reg);
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case 16:
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return ioread16(mapped_reg);
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case 32:
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return ioread32(mapped_reg);
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}
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BUG();
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return 0;
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}
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
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u32 data)
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{
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switch (reg_width) {
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case 8:
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iowrite8(data, mapped_reg);
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return;
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case 16:
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iowrite16(data, mapped_reg);
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return;
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case 32:
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iowrite32(data, mapped_reg);
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return;
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}
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BUG();
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}
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u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
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{
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return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
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}
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void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
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{
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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~data);
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sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int in_pos,
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void __iomem **mapped_regp, u32 *maskp,
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unsigned int *posp)
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{
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unsigned int k;
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*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
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if (crp->field_width) {
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*maskp = (1 << crp->field_width) - 1;
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*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
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} else {
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*maskp = (1 << crp->var_field_width[in_pos]) - 1;
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*posp = crp->reg_width;
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for (k = 0; k <= in_pos; k++)
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*posp -= crp->var_field_width[k];
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}
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}
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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int field, u32 value)
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{
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void __iomem *mapped_reg;
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unsigned int pos;
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u32 mask, data;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
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"r_width = %u, f_width = %u\n",
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crp->reg, value, field, crp->reg_width, crp->field_width);
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mask = ~(mask << pos);
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value = value << pos;
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data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
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data &= mask;
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data |= value;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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~data);
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
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const struct pinmux_cfg_reg **crp,
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unsigned int *fieldp, u32 *valuep)
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{
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unsigned int k = 0;
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while (1) {
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const struct pinmux_cfg_reg *config_reg =
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pfc->info->cfg_regs + k;
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unsigned int r_width = config_reg->reg_width;
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unsigned int f_width = config_reg->field_width;
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unsigned int curr_width;
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unsigned int bit_pos;
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unsigned int pos = 0;
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unsigned int m = 0;
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if (!r_width)
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break;
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for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
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u32 ncomb;
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u32 n;
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if (f_width)
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curr_width = f_width;
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else
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curr_width = config_reg->var_field_width[m];
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ncomb = 1 << curr_width;
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for (n = 0; n < ncomb; n++) {
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if (config_reg->enum_ids[pos + n] == enum_id) {
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*crp = config_reg;
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*fieldp = m;
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*valuep = n;
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return 0;
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}
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}
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pos += ncomb;
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m++;
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}
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k++;
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}
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return -EINVAL;
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}
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static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
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u16 *enum_idp)
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{
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const u16 *data = pfc->info->pinmux_data;
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unsigned int k;
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if (pos) {
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*enum_idp = data[pos + 1];
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return pos + 1;
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}
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for (k = 0; k < pfc->info->pinmux_data_size; k++) {
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if (data[k] == mark) {
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*enum_idp = data[k + 1];
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return k + 1;
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}
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}
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dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
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mark);
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return -EINVAL;
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}
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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{
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const struct pinmux_range *range;
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int pos = 0;
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switch (pinmux_type) {
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case PINMUX_TYPE_GPIO:
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case PINMUX_TYPE_FUNCTION:
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range = NULL;
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break;
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case PINMUX_TYPE_OUTPUT:
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range = &pfc->info->output;
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break;
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case PINMUX_TYPE_INPUT:
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range = &pfc->info->input;
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break;
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default:
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return -EINVAL;
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}
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/* Iterate over all the configuration fields we need to update. */
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while (1) {
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const struct pinmux_cfg_reg *cr;
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unsigned int field;
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u16 enum_id;
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u32 value;
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int in_range;
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int ret;
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pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
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if (pos < 0)
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return pos;
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if (!enum_id)
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break;
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/* Check if the configuration field selects a function. If it
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* doesn't, skip the field if it's not applicable to the
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* requested pinmux type.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
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if (!in_range) {
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if (pinmux_type == PINMUX_TYPE_FUNCTION) {
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/* Functions are allowed to modify all
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* fields.
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*/
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in_range = 1;
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} else if (pinmux_type != PINMUX_TYPE_GPIO) {
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/* Input/output types can only modify fields
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* that correspond to their respective ranges.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, range);
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/*
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* special case pass through for fixed
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* input-only or output-only pins without
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* function enum register association.
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*/
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if (in_range && enum_id == range->force)
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continue;
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}
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/* GPIOs are only allowed to modify function fields. */
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}
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if (!in_range)
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continue;
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ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
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if (ret < 0)
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return ret;
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sh_pfc_write_config_reg(pfc, cr, field, value);
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}
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return 0;
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}
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const struct pinmux_bias_reg *
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sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *bit)
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{
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unsigned int i, j;
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
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if (pfc->info->bias_regs[i].pins[j] == pin) {
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*bit = j;
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return &pfc->info->bias_regs[i];
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}
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}
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}
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WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
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return NULL;
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}
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static int sh_pfc_init_ranges(struct sh_pfc *pfc)
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{
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struct sh_pfc_pin_range *range;
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unsigned int nr_ranges;
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unsigned int i;
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if (pfc->info->pins[0].pin == (u16)-1) {
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/* Pin number -1 denotes that the SoC doesn't report pin numbers
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* in its pin arrays yet. Consider the pin numbers range as
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* continuous and allocate a single range.
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*/
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pfc->nr_ranges = 1;
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pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
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GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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pfc->ranges->start = 0;
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pfc->ranges->end = pfc->info->nr_pins - 1;
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pfc->nr_gpio_pins = pfc->info->nr_pins;
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return 0;
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}
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/* Count, allocate and fill the ranges. The PFC SoC data pins array must
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* be sorted by pin numbers, and pins without a GPIO port must come
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* last.
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*/
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for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
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nr_ranges++;
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}
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pfc->nr_ranges = nr_ranges;
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pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
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GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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range = pfc->ranges;
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range->start = pfc->info->pins[0].pin;
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for (i = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
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continue;
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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range++;
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range->start = pfc->info->pins[i].pin;
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}
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id sh_pfc_of_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_EMEV2
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{
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.compatible = "renesas,pfc-emev2",
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.data = &emev2_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A73A4
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{
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.compatible = "renesas,pfc-r8a73a4",
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.data = &r8a73a4_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7740
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{
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.compatible = "renesas,pfc-r8a7740",
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.data = &r8a7740_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7743
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{
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.compatible = "renesas,pfc-r8a7743",
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.data = &r8a7743_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7745
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{
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.compatible = "renesas,pfc-r8a7745",
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.data = &r8a7745_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7778
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{
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.compatible = "renesas,pfc-r8a7778",
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.data = &r8a7778_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7779
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{
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.compatible = "renesas,pfc-r8a7779",
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.data = &r8a7779_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7790
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{
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.compatible = "renesas,pfc-r8a7790",
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.data = &r8a7790_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7791
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{
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.compatible = "renesas,pfc-r8a7791",
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.data = &r8a7791_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7792
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{
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.compatible = "renesas,pfc-r8a7792",
|
|
.data = &r8a7792_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
|
{
|
|
.compatible = "renesas,pfc-r8a7793",
|
|
.data = &r8a7793_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
|
{
|
|
.compatible = "renesas,pfc-r8a7794",
|
|
.data = &r8a7794_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
|
{
|
|
.compatible = "renesas,pfc-r8a7795",
|
|
.data = &r8a7795_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
|
{
|
|
.compatible = "renesas,pfc-r8a7796",
|
|
.data = &r8a7796_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77995
|
|
{
|
|
.compatible = "renesas,pfc-r8a77995",
|
|
.data = &r8a77995_pinmux_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH73A0
|
|
{
|
|
.compatible = "renesas,pfc-sh73a0",
|
|
.data = &sh73a0_pinmux_info,
|
|
},
|
|
#endif
|
|
{ },
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
|
|
static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
|
|
{
|
|
}
|
|
|
|
static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
|
|
{
|
|
pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
|
|
}
|
|
|
|
static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
|
|
{
|
|
sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
|
|
}
|
|
|
|
static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
|
|
void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
|
|
{
|
|
unsigned int i, n = 0;
|
|
|
|
if (pfc->info->cfg_regs)
|
|
for (i = 0; pfc->info->cfg_regs[i].reg; i++)
|
|
do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
|
|
|
|
if (pfc->info->drive_regs)
|
|
for (i = 0; pfc->info->drive_regs[i].reg; i++)
|
|
do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
|
|
|
|
if (pfc->info->bias_regs)
|
|
for (i = 0; pfc->info->bias_regs[i].puen; i++) {
|
|
do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
|
|
if (pfc->info->bias_regs[i].pud)
|
|
do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
|
|
}
|
|
|
|
if (pfc->info->ioctrl_regs)
|
|
for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
|
|
do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
|
|
|
|
return n;
|
|
}
|
|
|
|
static int sh_pfc_suspend_init(struct sh_pfc *pfc)
|
|
{
|
|
unsigned int n;
|
|
|
|
/* This is the best we can do to check for the presence of PSCI */
|
|
if (!psci_ops.cpu_suspend)
|
|
return 0;
|
|
|
|
n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
|
|
if (!n)
|
|
return 0;
|
|
|
|
pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
|
|
sizeof(*pfc->saved_regs),
|
|
GFP_KERNEL);
|
|
if (!pfc->saved_regs)
|
|
return -ENOMEM;
|
|
|
|
dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
|
|
return 0;
|
|
}
|
|
|
|
static int sh_pfc_suspend_noirq(struct device *dev)
|
|
{
|
|
struct sh_pfc *pfc = dev_get_drvdata(dev);
|
|
|
|
if (pfc->saved_regs)
|
|
sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
|
|
return 0;
|
|
}
|
|
|
|
static int sh_pfc_resume_noirq(struct device *dev)
|
|
{
|
|
struct sh_pfc *pfc = dev_get_drvdata(dev);
|
|
|
|
if (pfc->saved_regs)
|
|
sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sh_pfc_pm = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
|
|
};
|
|
#define DEV_PM_OPS &sh_pfc_pm
|
|
#else
|
|
static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
|
|
#define DEV_PM_OPS NULL
|
|
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
|
|
|
|
static int sh_pfc_probe(struct platform_device *pdev)
|
|
{
|
|
#ifdef CONFIG_OF
|
|
struct device_node *np = pdev->dev.of_node;
|
|
#endif
|
|
const struct sh_pfc_soc_info *info;
|
|
struct sh_pfc *pfc;
|
|
int ret;
|
|
|
|
#ifdef CONFIG_OF
|
|
if (np)
|
|
info = of_device_get_match_data(&pdev->dev);
|
|
else
|
|
#endif
|
|
info = (const void *)platform_get_device_id(pdev)->driver_data;
|
|
|
|
pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
|
|
if (pfc == NULL)
|
|
return -ENOMEM;
|
|
|
|
pfc->info = info;
|
|
pfc->dev = &pdev->dev;
|
|
|
|
ret = sh_pfc_map_resources(pfc, pdev);
|
|
if (unlikely(ret < 0))
|
|
return ret;
|
|
|
|
spin_lock_init(&pfc->lock);
|
|
|
|
if (info->ops && info->ops->init) {
|
|
ret = info->ops->init(pfc);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* .init() may have overridden pfc->info */
|
|
info = pfc->info;
|
|
}
|
|
|
|
ret = sh_pfc_suspend_init(pfc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable dummy states for those platforms without pinctrl support */
|
|
if (!of_have_populated_dt())
|
|
pinctrl_provide_dummies();
|
|
|
|
ret = sh_pfc_init_ranges(pfc);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* Initialize pinctrl bindings first
|
|
*/
|
|
ret = sh_pfc_register_pinctrl(pfc);
|
|
if (unlikely(ret != 0))
|
|
return ret;
|
|
|
|
#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
|
|
/*
|
|
* Then the GPIO chip
|
|
*/
|
|
ret = sh_pfc_register_gpiochip(pfc);
|
|
if (unlikely(ret != 0)) {
|
|
/*
|
|
* If the GPIO chip fails to come up we still leave the
|
|
* PFC state as it is, given that there are already
|
|
* extant users of it that have succeeded by this point.
|
|
*/
|
|
dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
|
|
}
|
|
#endif
|
|
|
|
platform_set_drvdata(pdev, pfc);
|
|
|
|
dev_info(pfc->dev, "%s support registered\n", info->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id sh_pfc_id_table[] = {
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7203
|
|
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7264
|
|
{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7269
|
|
{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7720
|
|
{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7722
|
|
{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7723
|
|
{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7724
|
|
{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7734
|
|
{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7757
|
|
{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7785
|
|
{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SH7786
|
|
{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_SHX3
|
|
{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
|
|
#endif
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver sh_pfc_driver = {
|
|
.probe = sh_pfc_probe,
|
|
.id_table = sh_pfc_id_table,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = of_match_ptr(sh_pfc_of_table),
|
|
.pm = DEV_PM_OPS,
|
|
},
|
|
};
|
|
|
|
static int __init sh_pfc_init(void)
|
|
{
|
|
return platform_driver_register(&sh_pfc_driver);
|
|
}
|
|
postcore_initcall(sh_pfc_init);
|