618 lines
16 KiB
C
618 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Faraday Technology FTPC100 PCI Controller
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*
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on the out-of-tree OpenWRT patch for Cortina Gemini:
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* Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
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* Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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* Based on SL2312 PCI controller code
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* Storlink (C) 2003
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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/*
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* Special configuration registers directly in the first few words
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* in I/O space.
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*/
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#define PCI_IOSIZE 0x00
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#define PCI_PROT 0x04 /* AHB protection */
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#define PCI_CTRL 0x08 /* PCI control signal */
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#define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
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#define PCI_CONFIG 0x28 /* PCI configuration command register */
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#define PCI_DATA 0x2C
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#define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
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#define FARADAY_PCI_PMC 0x40 /* Power management control */
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#define FARADAY_PCI_PMCSR 0x44 /* Power management status */
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#define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
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#define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
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#define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
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#define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
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#define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
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#define PCI_STATUS_66MHZ_CAPABLE BIT(21)
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/* Bits 31..28 gives INTD..INTA status */
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#define PCI_CTRL2_INTSTS_SHIFT 28
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#define PCI_CTRL2_INTMASK_CMDERR BIT(27)
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#define PCI_CTRL2_INTMASK_PARERR BIT(26)
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/* Bits 25..22 masks INTD..INTA */
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#define PCI_CTRL2_INTMASK_SHIFT 22
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#define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
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#define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
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#define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
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#define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
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#define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
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#define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
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/* Bit 15 reserved */
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#define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
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#define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
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#define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
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#define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
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#define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
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#define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
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#define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
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/* Bits 7..4 reserved */
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/* Bits 3..0 TRDYW */
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/*
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* Memory configs:
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* Bit 31..20 defines the PCI side memory base
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* Bit 19..16 (4 bits) defines the size per below
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*/
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#define FARADAY_PCI_MEMBASE_MASK 0xfff00000
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#define FARADAY_PCI_MEMSIZE_1MB 0x0
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#define FARADAY_PCI_MEMSIZE_2MB 0x1
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#define FARADAY_PCI_MEMSIZE_4MB 0x2
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#define FARADAY_PCI_MEMSIZE_8MB 0x3
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#define FARADAY_PCI_MEMSIZE_16MB 0x4
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#define FARADAY_PCI_MEMSIZE_32MB 0x5
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#define FARADAY_PCI_MEMSIZE_64MB 0x6
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#define FARADAY_PCI_MEMSIZE_128MB 0x7
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#define FARADAY_PCI_MEMSIZE_256MB 0x8
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#define FARADAY_PCI_MEMSIZE_512MB 0x9
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#define FARADAY_PCI_MEMSIZE_1GB 0xa
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#define FARADAY_PCI_MEMSIZE_2GB 0xb
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#define FARADAY_PCI_MEMSIZE_SHIFT 16
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/*
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* The DMA base is set to 0x0 for all memory segments, it reflects the
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* fact that the memory of the host system starts at 0x0.
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*/
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#define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
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#define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
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#define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
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/* Defines for PCI configuration command register */
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#define PCI_CONF_ENABLE BIT(31)
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#define PCI_CONF_WHERE(r) ((r) & 0xFC)
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#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
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#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
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#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
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/**
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* struct faraday_pci_variant - encodes IP block differences
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* @cascaded_irq: this host has cascaded IRQs from an interrupt controller
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* embedded in the host bridge.
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*/
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struct faraday_pci_variant {
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bool cascaded_irq;
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};
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struct faraday_pci {
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struct device *dev;
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void __iomem *base;
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struct irq_domain *irqdomain;
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struct pci_bus *bus;
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struct clk *bus_clk;
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};
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static int faraday_res_to_memcfg(resource_size_t mem_base,
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resource_size_t mem_size, u32 *val)
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{
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u32 outval;
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switch (mem_size) {
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case SZ_1M:
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outval = FARADAY_PCI_MEMSIZE_1MB;
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break;
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case SZ_2M:
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outval = FARADAY_PCI_MEMSIZE_2MB;
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break;
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case SZ_4M:
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outval = FARADAY_PCI_MEMSIZE_4MB;
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break;
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case SZ_8M:
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outval = FARADAY_PCI_MEMSIZE_8MB;
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break;
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case SZ_16M:
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outval = FARADAY_PCI_MEMSIZE_16MB;
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break;
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case SZ_32M:
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outval = FARADAY_PCI_MEMSIZE_32MB;
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break;
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case SZ_64M:
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outval = FARADAY_PCI_MEMSIZE_64MB;
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break;
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case SZ_128M:
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outval = FARADAY_PCI_MEMSIZE_128MB;
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break;
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case SZ_256M:
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outval = FARADAY_PCI_MEMSIZE_256MB;
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break;
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case SZ_512M:
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outval = FARADAY_PCI_MEMSIZE_512MB;
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break;
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case SZ_1G:
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outval = FARADAY_PCI_MEMSIZE_1GB;
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break;
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case SZ_2G:
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outval = FARADAY_PCI_MEMSIZE_2GB;
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break;
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default:
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return -EINVAL;
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}
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outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
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/* This is probably not good */
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if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
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pr_warn("truncated PCI memory base\n");
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/* Translate to bridge side address space */
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outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
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pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
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&mem_base, &mem_size, outval);
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*val = outval;
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return 0;
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}
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static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
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unsigned int fn, int config, int size,
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u32 *value)
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{
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writel(PCI_CONF_BUS(bus_number) |
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PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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p->base + PCI_CONFIG);
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*value = readl(p->base + PCI_DATA);
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if (size == 1)
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*value = (*value >> (8 * (config & 3))) & 0xFF;
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else if (size == 2)
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*value = (*value >> (8 * (config & 3))) & 0xFFFF;
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return PCIBIOS_SUCCESSFUL;
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}
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static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
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int config, int size, u32 *value)
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{
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struct faraday_pci *p = bus->sysdata;
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dev_dbg(&bus->dev,
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"[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
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PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
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return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
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}
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static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
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unsigned int fn, int config, int size,
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u32 value)
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{
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int ret = PCIBIOS_SUCCESSFUL;
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writel(PCI_CONF_BUS(bus_number) |
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PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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p->base + PCI_CONFIG);
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switch (size) {
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case 4:
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writel(value, p->base + PCI_DATA);
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break;
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case 2:
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writew(value, p->base + PCI_DATA + (config & 3));
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break;
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case 1:
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writeb(value, p->base + PCI_DATA + (config & 3));
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break;
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default:
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ret = PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return ret;
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}
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static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
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int config, int size, u32 value)
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{
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struct faraday_pci *p = bus->sysdata;
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dev_dbg(&bus->dev,
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"[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
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PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
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return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
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value);
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}
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static struct pci_ops faraday_pci_ops = {
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.read = faraday_pci_read_config,
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.write = faraday_pci_write_config,
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};
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static void faraday_pci_ack_irq(struct irq_data *d)
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{
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struct faraday_pci *p = irq_data_get_irq_chip_data(d);
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unsigned int reg;
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faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
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reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
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reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
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faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
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}
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static void faraday_pci_mask_irq(struct irq_data *d)
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{
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struct faraday_pci *p = irq_data_get_irq_chip_data(d);
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unsigned int reg;
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faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
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reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
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| BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
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faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
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}
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static void faraday_pci_unmask_irq(struct irq_data *d)
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{
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struct faraday_pci *p = irq_data_get_irq_chip_data(d);
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unsigned int reg;
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faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
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reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
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reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
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faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
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}
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static void faraday_pci_irq_handler(struct irq_desc *desc)
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{
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struct faraday_pci *p = irq_desc_get_handler_data(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned int irq_stat, reg, i;
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faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
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irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
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chained_irq_enter(irqchip, desc);
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for (i = 0; i < 4; i++) {
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if ((irq_stat & BIT(i)) == 0)
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continue;
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generic_handle_irq(irq_find_mapping(p->irqdomain, i));
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}
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chained_irq_exit(irqchip, desc);
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}
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static struct irq_chip faraday_pci_irq_chip = {
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.name = "PCI",
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.irq_ack = faraday_pci_ack_irq,
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.irq_mask = faraday_pci_mask_irq,
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.irq_unmask = faraday_pci_unmask_irq,
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};
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static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
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.map = faraday_pci_irq_map,
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};
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static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
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{
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struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
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int irq;
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int i;
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if (!intc) {
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dev_err(p->dev, "missing child interrupt-controller node\n");
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return -EINVAL;
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}
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/* All PCI IRQs cascade off this one */
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irq = of_irq_get(intc, 0);
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if (irq <= 0) {
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dev_err(p->dev, "failed to get parent IRQ\n");
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return irq ?: -EINVAL;
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}
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p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
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&faraday_pci_irqdomain_ops, p);
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if (!p->irqdomain) {
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dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
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return -EINVAL;
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}
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irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
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for (i = 0; i < 4; i++)
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irq_create_mapping(p->irqdomain, i);
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return 0;
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}
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static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
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struct device_node *np)
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{
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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struct device *dev = p->dev;
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u32 confreg[3] = {
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FARADAY_PCI_MEM1_BASE_SIZE,
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FARADAY_PCI_MEM2_BASE_SIZE,
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FARADAY_PCI_MEM3_BASE_SIZE,
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};
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int i = 0;
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u32 val;
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if (of_pci_dma_range_parser_init(&parser, np)) {
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dev_err(dev, "missing dma-ranges property\n");
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return -EINVAL;
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}
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/*
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* Get the dma-ranges from the device tree
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*/
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for_each_of_pci_range(&parser, &range) {
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u64 end = range.pci_addr + range.size - 1;
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int ret;
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ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
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if (ret) {
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dev_err(dev,
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"DMA range %d: illegal MEM resource size\n", i);
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return -EINVAL;
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}
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dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
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i + 1, range.pci_addr, end, val);
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if (i <= 2) {
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faraday_raw_pci_write_config(p, 0, 0, confreg[i],
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4, val);
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} else {
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dev_err(dev, "ignore extraneous dma-range %d\n", i);
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break;
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}
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i++;
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}
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return 0;
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}
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static int faraday_pci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct faraday_pci_variant *variant =
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of_device_get_match_data(dev);
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struct resource *regs;
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resource_size_t io_base;
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struct resource_entry *win;
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struct faraday_pci *p;
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struct resource *mem;
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struct resource *io;
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struct pci_host_bridge *host;
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struct clk *clk;
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unsigned char max_bus_speed = PCI_SPEED_33MHz;
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unsigned char cur_bus_speed = PCI_SPEED_33MHz;
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int ret;
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u32 val;
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LIST_HEAD(res);
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host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
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if (!host)
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return -ENOMEM;
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host->dev.parent = dev;
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host->ops = &faraday_pci_ops;
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host->busnr = 0;
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host->msi = NULL;
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host->map_irq = of_irq_parse_and_map_pci;
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host->swizzle_irq = pci_common_swizzle;
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p = pci_host_bridge_priv(host);
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host->sysdata = p;
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p->dev = dev;
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/* Retrieve and enable optional clocks */
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clk = devm_clk_get(dev, "PCLK");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "could not prepare PCLK\n");
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return ret;
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}
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p->bus_clk = devm_clk_get(dev, "PCICLK");
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if (IS_ERR(p->bus_clk))
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return PTR_ERR(p->bus_clk);
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|
ret = clk_prepare_enable(p->bus_clk);
|
|
if (ret) {
|
|
dev_err(dev, "could not prepare PCICLK\n");
|
|
return ret;
|
|
}
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
p->base = devm_ioremap_resource(dev, regs);
|
|
if (IS_ERR(p->base))
|
|
return PTR_ERR(p->base);
|
|
|
|
ret = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
|
|
&res, &io_base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_pci_bus_resources(dev, &res);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Get the I/O and memory ranges from DT */
|
|
resource_list_for_each_entry(win, &res) {
|
|
switch (resource_type(win->res)) {
|
|
case IORESOURCE_IO:
|
|
io = win->res;
|
|
io->name = "Gemini PCI I/O";
|
|
if (!faraday_res_to_memcfg(io->start - win->offset,
|
|
resource_size(io), &val)) {
|
|
/* setup I/O space size */
|
|
writel(val, p->base + PCI_IOSIZE);
|
|
} else {
|
|
dev_err(dev, "illegal IO mem size\n");
|
|
return -EINVAL;
|
|
}
|
|
ret = pci_remap_iospace(io, io_base);
|
|
if (ret) {
|
|
dev_warn(dev, "error %d: failed to map resource %pR\n",
|
|
ret, io);
|
|
continue;
|
|
}
|
|
break;
|
|
case IORESOURCE_MEM:
|
|
mem = win->res;
|
|
mem->name = "Gemini PCI MEM";
|
|
break;
|
|
case IORESOURCE_BUS:
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Setup hostbridge */
|
|
val = readl(p->base + PCI_CTRL);
|
|
val |= PCI_COMMAND_IO;
|
|
val |= PCI_COMMAND_MEMORY;
|
|
val |= PCI_COMMAND_MASTER;
|
|
writel(val, p->base + PCI_CTRL);
|
|
/* Mask and clear all interrupts */
|
|
faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
|
|
if (variant->cascaded_irq) {
|
|
ret = faraday_pci_setup_cascaded_irq(p);
|
|
if (ret) {
|
|
dev_err(dev, "failed to setup cascaded IRQ\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Check bus clock if we can gear up to 66 MHz */
|
|
if (!IS_ERR(p->bus_clk)) {
|
|
unsigned long rate;
|
|
u32 val;
|
|
|
|
faraday_raw_pci_read_config(p, 0, 0,
|
|
FARADAY_PCI_STATUS_CMD, 4, &val);
|
|
rate = clk_get_rate(p->bus_clk);
|
|
|
|
if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
|
|
dev_info(dev, "33MHz bus is 66MHz capable\n");
|
|
max_bus_speed = PCI_SPEED_66MHz;
|
|
ret = clk_set_rate(p->bus_clk, 66000000);
|
|
if (ret)
|
|
dev_err(dev, "failed to set bus clock\n");
|
|
} else {
|
|
dev_info(dev, "33MHz only bus\n");
|
|
max_bus_speed = PCI_SPEED_33MHz;
|
|
}
|
|
|
|
/* Bumping the clock may fail so read back the rate */
|
|
rate = clk_get_rate(p->bus_clk);
|
|
if (rate == 33000000)
|
|
cur_bus_speed = PCI_SPEED_33MHz;
|
|
if (rate == 66000000)
|
|
cur_bus_speed = PCI_SPEED_66MHz;
|
|
}
|
|
|
|
ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
list_splice_init(&res, &host->windows);
|
|
ret = pci_scan_root_bus_bridge(host);
|
|
if (ret) {
|
|
dev_err(dev, "failed to scan host: %d\n", ret);
|
|
return ret;
|
|
}
|
|
p->bus = host->bus;
|
|
p->bus->max_bus_speed = max_bus_speed;
|
|
p->bus->cur_bus_speed = cur_bus_speed;
|
|
|
|
pci_bus_assign_resources(p->bus);
|
|
pci_bus_add_devices(p->bus);
|
|
pci_free_resource_list(&res);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We encode bridge variants here, we have at least two so it doesn't
|
|
* hurt to have infrastructure to encompass future variants as well.
|
|
*/
|
|
const struct faraday_pci_variant faraday_regular = {
|
|
.cascaded_irq = true,
|
|
};
|
|
|
|
const struct faraday_pci_variant faraday_dual = {
|
|
.cascaded_irq = false,
|
|
};
|
|
|
|
static const struct of_device_id faraday_pci_of_match[] = {
|
|
{
|
|
.compatible = "faraday,ftpci100",
|
|
.data = &faraday_regular,
|
|
},
|
|
{
|
|
.compatible = "faraday,ftpci100-dual",
|
|
.data = &faraday_dual,
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver faraday_pci_driver = {
|
|
.driver = {
|
|
.name = "ftpci100",
|
|
.of_match_table = of_match_ptr(faraday_pci_of_match),
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = faraday_pci_probe,
|
|
};
|
|
builtin_platform_driver(faraday_pci_driver);
|