158 lines
3.8 KiB
C
158 lines
3.8 KiB
C
/*
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* Copyright (c) 2015-2016 Quantenna Communications, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _QTN_FMAC_PCIE_IPC_H_
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#define _QTN_FMAC_PCIE_IPC_H_
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#include <linux/types.h>
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#include "shm_ipc_defs.h"
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/* bitmap for EP status and flags: updated by EP, read by RC */
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#define QTN_EP_HAS_UBOOT BIT(0)
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#define QTN_EP_HAS_FIRMWARE BIT(1)
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#define QTN_EP_REQ_UBOOT BIT(2)
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#define QTN_EP_REQ_FIRMWARE BIT(3)
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#define QTN_EP_ERROR_UBOOT BIT(4)
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#define QTN_EP_ERROR_FIRMWARE BIT(5)
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#define QTN_EP_FW_LOADRDY BIT(8)
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#define QTN_EP_FW_SYNC BIT(9)
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#define QTN_EP_FW_RETRY BIT(10)
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#define QTN_EP_FW_QLINK_DONE BIT(15)
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#define QTN_EP_FW_DONE BIT(16)
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/* bitmap for RC status and flags: updated by RC, read by EP */
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#define QTN_RC_PCIE_LINK BIT(0)
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#define QTN_RC_NET_LINK BIT(1)
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#define QTN_RC_FW_FLASHBOOT BIT(5)
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#define QTN_RC_FW_QLINK BIT(7)
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#define QTN_RC_FW_LOADRDY BIT(8)
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#define QTN_RC_FW_SYNC BIT(9)
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/* state transition timeouts */
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#define QTN_FW_DL_TIMEOUT_MS 3000
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#define QTN_FW_QLINK_TIMEOUT_MS 30000
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#define PCIE_HDP_INT_RX_BITS (0 \
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| PCIE_HDP_INT_EP_TXDMA \
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| PCIE_HDP_INT_EP_TXEMPTY \
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| PCIE_HDP_INT_HHBM_UF \
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)
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#define PCIE_HDP_INT_TX_BITS (0 \
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| PCIE_HDP_INT_EP_RXDMA \
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)
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32))
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#define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL))
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#define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l))
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#else
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#define QTN_HOST_HI32(a) 0
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#define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL))
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#define QTN_HOST_ADDR(h, l) ((u32)l)
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#endif
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#define QTN_SYSCTL_BAR 0
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#define QTN_SHMEM_BAR 2
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#define QTN_DMA_BAR 3
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#define QTN_PCIE_BDA_VERSION 0x1002
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#define PCIE_BDA_NAMELEN 32
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#define PCIE_HHBM_MAX_SIZE 2048
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#define SKB_BUF_SIZE 2048
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#define QTN_PCIE_BOARDFLG "PCIEQTN"
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#define QTN_PCIE_FW_DLMASK 0xF
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#define QTN_PCIE_FW_BUFSZ 2048
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#define QTN_ENET_ADDR_LENGTH 6
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#define QTN_TXDONE_MASK ((u32)0x80000000)
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#define QTN_GET_LEN(x) ((x) & 0xFFFF)
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#define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF
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#define QTN_PCIE_TX_DESC_LEN_SHIFT 0
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#define QTN_PCIE_TX_DESC_PORT_MASK 0xF
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#define QTN_PCIE_TX_DESC_PORT_SHIFT 16
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#define QTN_PCIE_TX_DESC_TQE_BIT BIT(24)
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#define QTN_EP_LHOST_TQE_PORT 4
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enum qtnf_pcie_bda_ipc_flags {
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QTN_PCIE_IPC_FLAG_HBM_MAGIC = BIT(0),
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QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1),
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};
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struct qtnf_pcie_bda {
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__le16 bda_len;
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__le16 bda_version;
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__le32 bda_pci_endian;
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__le32 bda_ep_state;
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__le32 bda_rc_state;
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__le32 bda_dma_mask;
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__le32 bda_msi_addr;
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__le32 bda_flashsz;
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u8 bda_boardname[PCIE_BDA_NAMELEN];
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__le32 bda_rc_msi_enabled;
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u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE];
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__le32 bda_dsbw_start_index;
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__le32 bda_dsbw_end_index;
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__le32 bda_dsbw_total_bytes;
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__le32 bda_rc_tx_bd_base;
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__le32 bda_rc_tx_bd_num;
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u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH];
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struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
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struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */
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} __packed;
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struct qtnf_tx_bd {
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__le32 addr;
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__le32 addr_h;
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__le32 info;
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__le32 info_h;
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} __packed;
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struct qtnf_rx_bd {
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__le32 addr;
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__le32 addr_h;
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__le32 info;
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__le32 info_h;
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__le32 next_ptr;
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__le32 next_ptr_h;
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} __packed;
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enum qtnf_fw_loadtype {
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QTN_FW_DBEGIN,
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QTN_FW_DSUB,
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QTN_FW_DEND,
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QTN_FW_CTRL
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};
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struct qtnf_pcie_fw_hdr {
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u8 boardflg[8];
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__le32 fwsize;
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__le32 seqnum;
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__le32 type;
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__le32 pktlen;
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__le32 crc;
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} __packed;
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#endif /* _QTN_FMAC_PCIE_IPC_H_ */
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